Thales deployed the DO-254/ED-80 CTS (Compliance Tool Set) from Aldec. The DO-254/ED-80 CTS is an In-Hardware FPGA validation system developed to meet Level A-D requirements defined by the DO-254/ED-80 Design Assurance Guidance for Airborne Electronic Certification Manual. The deployment of the system has enabled Thales to validate for the certification authorities that the hardware implementation of an advanced avionics system’s RTL design is working correctly at the required speed in the targeted FPGA. Thales’ design involved an Altera Cyclone® II FPGA with multiple clocks and speeds in excess of 128MHz.
Aldec’s DO-254/ED-80 CTS enabled Thales engineers to uncover and resolve design problems that were not visible using an event-driven HDL software simulator. Aldec’s DO-254/ED-80 CTS utilized the actual end-target FPGA device and enabled the reuse of the same test vectors as for RTL simulation in order to validate that the designs operation in the final target hardware met the actual system speed requirements without the need for additional analysis as is the case with other verification solutions or prototyping. Utilizing the same test vectors for each stage of the design verification, Aldec’s DO-254/ED-80 CTS delivered time savings for requirements traceability and results analysis. The results from each of the tests were stored and documented to be used in the certification process as required by the DO-254/ED-80 Certification Manual. Furthermore, Aldec provided a full set of the tool tests for the qualification process according to DO-254/ED-80 specification.
The DO-254/ED-80 CTS solution from Aldec provides support for Levels A through D of the “Design Assurance Guidance for Airborne Electronic Hardware” (DO-254/ED-80) Chapter 6.2 “Verification Process” and Chapter 11.4 “Tool Assessment and Qualification Process.” The DO-254/ED-80 CTS consists of a mixed language HDL Simulation tool suite and In-Hardware Simulation system that supports the customer’s specific FPGA, PLD, or ASIC target device providing functional verification and/or at-speed testing.
The verification flow requires the design first be checked in the HDL simulator to validate design’s functionality against requirements and then in the end-target FPGA hardware. A golden set of waveform vectors validated in the HDL simulation are automatically compared with the set of waveform vectors generated after in-hardware simulation in the end-target FPGA device. In-hardware testing provides assurance that the design works in the target device just as it did during HDL simulation, with full traceability of the hardware outputs back to the design requirements.