Xilinx, Inc. (Nasdaq: XLNX) introduced a Digital Front End (DFE) design optimized for faster, lower cost development of 3rd Generation Partnership Protocol (3GPP) Long Term Evolution (LTE) wireless communications systems. It is the first DFE design specifically targeted for high performance 3GPP LTE radio applications that reduces overall power consumption and is scalable from large multi-sector macrocell to picocell base stations. The 3GPP LTE reference design is delivered with a comprehensive application note and design files for Virtex-5 device architectures, test vectors and scripts that enable designers to quickly evaluate the design performance in The MathWorks MATLAB(R) environment. Instructions for integrating the reference design into the target system design are also included. The design files, application note and integration instructions can be downloaded free of charge.
The Xilinx(R) 3GPP LTE design supports a fully featured programmable development platform using Xilinx Virtex(R)-5 FPGAs, the industry’s most widely adopted high-performance FPGA family. The LTE DFE platform consists of highly optimized blocks for Digital Up Conversion (DUC), Digital Down Conversion (DDC) and Crest Factor Reduction (CFR) that together form a complete LTE radio subsystem. It is compatible with existing Digital Pre-Distortion (DPD) designs from Xilinx, enabling systems architects to rapidly develop and integrate all the digital system elements of a high performance, commercial LTE system, and in a significantly shorter period of time than is feasible with traditional application-specific standard part (ASSP) and application-specific integrated circuit (ASIC) design methods, of which there are none currently available supporting LTE systems.
More info: LTE Digital Front End Reference Design