Lattice Semiconductor introduced the ispClock5400D family of differential clock distribution ICs. The ispClock5400D features the CleanClock ultra-low phase noise PLL. The ispClock5400D family consists of the six-output ispClock5406D and ten-output ispClock5410D. The FlexiClock output section of the ispClock5400D devices supports multiple logic standards and dual skew control features. The configuration of each device is held in on-chip non-volatile memory that is reprogrammable through a JTAG interface. Certain aspects of the device can be modified on the fly via an I2C interface. Samples of the ispClock5406D device (48-pin QFNS package) and ispClock5410D device (64-pin QFNS package) are available immediately. The ispClock5406D device is priced at $3.95 and the ispClock5410D device is priced at $5.50 in 1000 piece volumes.
The ispClock5400D family enables designers to reduce cost and complexity in their differential clock networks while providing the flexibility for late design changes, even after board assembly. The ispClock5400D devices are ideal for supplying high quality reference clocks to high speed serialized communication ICs that use SERDES technology, and the consolidation of components, such as fan-out buffers and zero-delay buffers, typically used for distributing high frequency clocks in a circuit board.
The ispClock5400D devices integrate an ultra-low phase noise CleanClock PLL, including an on-chip programmable analog filter and a programmable VCO with input clock frequencies up to 400MHz. The PAC-Designer software tool automatically determines the parameters of the PLL depending on the input and output clock frequencies. This wide band CleanClock PLL is compatible with the Spreadspectrum clocks required for distributing PCI Express and SATA clocks. The phase noise of the PLL is low enough to be suitable for sourcing clocks to SERDES chips.
The ispClock5400 family provides in-system programmable FlexiClock differential outputs. Each output can be configured to interface with a number of logic standards such as LVDS, MLVDS, HCSL, LVPECL, HSTL and SSTL. The output clock can be individually skewed using the phase angle and time skew mechanisms. In addition, the skew can be changed dynamically in-system through an I2C interface.
Timing Adjustments after Board Assembly
The configuration of each device is held in on-chip non-volatile memory that is reprogrammable through a JTAG interface. Certain aspects of the device can be modified on the fly via an I2C interface. Design for the devices is supported in the Lattice PAC-Designer software tool.
More info: ispClock 5400D Family (pdf)