Lattice Diamond v1.3 Design Software for Lattice FPGA Devices

Lattice Semiconductor introduced version 1.3 of the Lattice Diamond design software for Lattice FPGA products. Lattice Diamond v1.3 features clock jitter analysis and support for Lattice’s PAC-Designer 6.1 mixed signal design tools. Lattice Diamond v1.3 software is available now for download for both Windows and Linux. Once downloaded and installed, the software can be used with either the Lattice Diamond free license or the Lattice Diamond subscription license ($895 per year).

Lattice Diamond v1.3 Features

  • Designers can now add user-defined clock jitter to their design’s clocks while they are performing static timing analysis of the designs
  • Integrated with Lattice’s PAC-Designer 6.1 mixed signal design tools
  • Enhanced support for the MachXO2 device family
  • Includes updated timing and power analysis device information
  • Provides final production SSO models and bit streams for the LCMXO2-1200 and LCMXO2-1200U devices
  • FMax improvement of 5% to 15% on most designs targeted to the LCMXO2 devices
  • Supports a wafer-level package for the LCMXO2-2000U
  • Users control the amount of clock jitter they want to model on the clock signal through an extension to the existing timing preferences
  • Analysis results displayed in both the Trace report and the Timing Analysis View
  • Timing Analysis View rapidly updates the analysis results when the clock jitter is changed
  • Aids designers who want to migrate their designs to a lower cost device within the same device family while preserving the current package and board layout
  • Projects can now support complex multi-file testbenches and allow multiple design representations for the same design block
  • Simulation wizard can automatically determine which files should be set to simulation and pass the correct options to the simulator
  • Synthesis design constraints flow is now more intuitive and allows for multiple files that can be managed similar to the back-end preference files
  • When using the Reveal Analyzer, engineers can now download large trace data amounts and configure complex trigger setups more than 10 times faster than previously possible
  • Provides device resource utilization for each logical level of the design hierarchy following synthesis
  • Enables designers to make early design decisions about how to structure their design so that they can optimize utilization of the overall device
  • Designers can now select the best run when using parallel processing of the multiple implementations provided by Run Manager
  • Users can now directly select the active implementation in Run Manager and also control which one of the multi-par runs
  • New Diamond Programmer fully supports the direct programming features of the ispVM System

More info: Lattice Semiconductor