Altera’s RapidIO MegaCore function (version 9.0) has successfully passed RIOLAB’s Device Interoperability Level-3 (DIL-3) testing. Altera is the first FPGA vendor to offer a Serial RapidIO intellectual property (IP) core that is fully qualified by RIOLAB. Passing RIOLAB’s DIL testing gives system designers the added confidence that Altera’s devices and RapidIO IP core are compatible and interoperable within their RapidIO system. The Serial RapidIO MegaCore function is available for download as part of the combined Quartus II Software/Altera MegaCore release. The IP core is available as encrypted IP or as source code for complete user control.
Altera’s Serial RapidIO MegaCore function is designed to the RapidIO interconnect specification version 1.3. The core supports x1 and x4 lane widths at 1.25-Gbps, 2.5-Gbps and 3.125-Gbps lane rates, and allows for physical-, transport- and logical-layer separation. The endpoint IP core comes complete with test benches that provide proven interoperability with leading digital signal processor and switch vendors.
RIOLAB is the world’s only independent RapidIO interoperability testing facility. DIL-3 is RIOLAB’s final stage of device interoperability testing and ensures Altera’s internally developed Serial RapidIO IP is interoperable with components, systems and software using RapidIO technology. The IP core works with Altera’s Arria, Cyclone and Stratix FPGAs and HardCopy ASICs.
More information: Altera Download Center