Through Silicon Vias, Signal Integrity, Design Methodologies, FPGA SoC

At DesignCon 2011, Xilinx experts will share insights about overcoming design challenges, improving signal integrity problems, understanding Through Silicon Via (TSV) processes, and meeting chip to chip I/O demands. Xilinx will also be exhibiting demos with MoSys, SiSoft, and Agilent. The demos will feature Xilinx’s Virtex-6 HXT FPGA. DesignCon is a design engineering event that addresses the challenges facing the semiconductor and electronic design engineer communities and provides solutions that can be implement immediately in designs. DesignCon 2011 is taking in Santa Clara, California through February 3, 2011.

Xilinx at DesignCon 2011

Entering the Era of Crossover SoCs
Global consumer markets continue to drive the need for ubiquitous computing and an insatiable thirst for communications bandwidth, which are fueling the growth of the electronics industry. Yet the cost of building custom SoCs to support many of the emerging applications is becoming increasingly difficult to justify – except for the highest volume devices. Rising to this challenge, a new class of crossover SoCs is emerging that combines many of the strengths of custom SoCs and FPGAs in a single device. In this session we will discuss the different approaches underway in the industry, including embedded processing subsystems, 3D interconnect technology, SiP and others, and how they will reshape the device landscape over the next decade.

FPGA Caveman meets FPGA Chiphead FPGA Design Tools and Methodologies: Can they keep pace?
This panel will discuss the performance and capabilities of 28nm FPGA devices and how FPGA vendors are providing ways for end users to integrate IP into FPGA architectures. This panel will examine the key pain points in the FPGA design process, look at unique design needs, and discuss new design tools, methodologies as well as the greater opportunity for a true commercial FPGA EDA tool industry.

How to Avoid Butchering S Parameters
This panel will discuss ways to avoid producing bad quality S parameter files for high speed serial channels. Specific topics will include causality, passivity, reciprocity, de-embedding, reference planes, and measurement techniques. Through a discussion of the advantages and disadvantages of each point of view, attendees will gain a broader understanding of S parameters in general and what it takes to produce good S parameter files.

Back to Edison, Back to Innovation
Inspired by the June 5, 2010 issue of TIME magazine, which recounted the impact of Thomas Edison’s idea factory and his relevance today, this panel will provide a modern look at Edison’s approach to ideas and results — a minor invention every 10 days and a big thing every six months or so — taken from the January 3, 1888 page in Edison’s idea book.

Meeting chip to chip I/O demands of 100G and beyond line cards
This panel will discuss trends and alternative solutions for interconnecting chips on 100 Gbps and beyond line cards that maximize throughput while minimizing pin count, die area and power.

Designing FPGA based PCBs
This panel will discuss the problems of designing FPGA based PCBs. The panel will address the designer challenges of optimizing the FPGA design across multiple domains, schematics and FPGA timing and explore ways to solve them.

Through Silicon Via Design Considering Technology Challenges
Xilinx will present a paper on a new approach for successful implementation of TSV for multi-gigabit or tens-of-gigabit per second SerDes application, possible mechanical and reliability issues on TSV process, and will also cover technology requirements and common challenges.

More info: DesignCon 2011 | Xilinx