DDR PHY Interface Compatible DDR2 SDRAM PHY

Tokyo Electron Device, Ltd. (TED) and Denali Software developed a DDR2 SDRAM PHY design on Xilinx’s Virtex-5 FPGA. The design is compatible with DDR PHY Interface (DFI), which is the industry standard interface for DDR memory controller and PHY. TED ASIC customers now have access to DDR PHY designs, in 90-nm process technologies and below, that integrate seamlessly with other DFI compatible designs, including Denali’s Databahn(TM) DDR memory controller products.

DDR2 SDRAM PHY helps to develop LSI faster with less risk using a high-speed DDR2 interface, relieving developers of time-consuming development and integration tasks needed for special designing of the DDR memory controller. Combining DDR2 SDRAM PHY and Denali’s Databahn memory controller design IP, featuring technology proven in LSI implementation and Tokyo Electron Device’s “inrevium(TM)” brand “Virtex-5 Multi-Application Evaluation Platform (TB-5V-LX110/220/330-DDR2),” developers can effectively improve the time-to-market cycle.

The goal of the DFI specification is to define a common interface between the memory controller logic and the PHY interface in order to reduce cost, time-to-market, and increase the potential for reuse of the individual components that make up the memory system. The DFI specification is being developed by expert contributors from recognized leaders in the semiconductor, IP and electronic design automation (EDA) industries, including: ARM, Denali, Intel, Rambus, Samsung, and Synopsys.

The DFI specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices. The DFI Specification Rev 1.0 was released for production development in January 2007, and is available online.

More info:
Denali, Tokyo Electron Device Create DFI DDR2 SDRAM PHY for Xilinx FPGA
Denali Software
Tokyo Electron Device
DFI Specification