Reflex CES (Custom Embedded Systems) introduced the Aurora-like IP core. It is based on Altera FPGA devices. The Reflex CES IP core enables interoperability between Xilinx Virtex-6 LXT and Altera Stratix IV and Stratix V GX FPGAs. The Reflex CES Aurora-like 8B/10B IP Core is available now with VHDL source code, test-benches, a reference design and user guide. Reflex CES plans to ship an Aurora-like IP Core that supports communication between FPGAs with a 64B/66B protocol at 10 Gbps.
The Reflex CES IP core is based on the Aurora 8B/10B, which is an open standard protocol used to transport data with higher connectivity performance for chip-to-chip and board-to-board architecture. The Aurora-like IP Core enables engineers to move data from point-to-point across one to sixteen serial lanes at 3.125 Gbps.
The IP core offers user flow control, native flow control, immediate and completion mode, and modules to convert interfaces to and from streaming Advanced eXtensible Interfaces (AXI). The low protocol overhead core features minimal data rate transfer latency with minimal logic resources — less than 900 equivalent logic cells for a 1 lane configuration — for cost effective implementation.
The Reflex CES Aurora-like IP Core is ideal for telecommunications/networking applications. It offers a fully compliant implementation of the Xilinx Aurora 8B/10B scalable, link-layer protocol for high-speed serial communication, and allows for communication between FPGAs through a backplane.
Reflex CES Aurora-like IP Core Features
- Up to 3.125Gbps bit rate per lane
- Configurable up to 16 transceivers lanes
- 8B/10B encoding
- Native flow control with immediate and completion mode
- User flow control
- Additional modules to convert interfaces to and from AXI streaming
- Full-duplex operation
- Framing interface for user data
- Clock compensation sequence generation
- Per lane polarity inversion
- Skew compensation
More info: Reflex CES Aurora-like IP Core (pdf)