Zuken, the engineering consulting company, and Aldec, the HDL verification specialists, formed a partnership to offer a combined design and verification flow for flexible field programmable gate array (FPGA) devices on printed circuit boards (PCBs). The partnership will focus integration efforts on Zuken’s enterprise-wide PCB design suite, CR-5000.
The increased density, higher performance and flexibility of FPGA devices has driven a growth in their market share over that of ASICs in recent years. But the versatility and huge gate count of the latest FPGAs introduces design challenges associated with library management, data sharing, revision control and mixed VHDL, Verilog, SystemC and SystemVerilog simulation; demanding that the complete PCB and FPGA design and verification process be harmonized.
The partnershop will enable designers to launch Aldec’s mixed language simulation technology from within CR-5000 System Designer for access to project-specific design data. It will be possible to perform FPGA timing simulation for the complete design rather than for the individual FPGAs in isolation. Additionally, within CR-5000 Board Designer, layout engineers will be able to perform pin swaps that will concurrently update all PCB and FPGA design data, rather than only be able to perform this on request from the FPGA implementation engineer.
» Zuken, Aldec Offer Design and Verification Flow for FPGA