Altera unveiled version 9.1 of their Quartus II software for CPLD, FPGA and HardCopy ASIC designs. Both the Subscription Edition and the free Web Edition of the Quartus II software version 9.1 are currently available for download. Quartus II software subscribers receive the ModelSim Altera Starter Edition and a full license to the IP Base Suite, which includes 14 of Altera’s most popular IP (DSP and memory) cores. The annual software subscription is $2,495 for a node-locked PC license and is available for purchase at Altera’s eStore or from authorized distributors.
Quartus II software v9.1 reduces compile times 20% versus the previous software release, while continuing to deliver on average 2X to 3X faster compile times compared to competing high-density 40-nm and 65-nm designs. New to the software is a Rapid Recompile feature, which significantly improves compile times for small design changes, as well as support for Altera’s newly announced Cyclone IV FPGAs. The compile time advantages in the latest release are driven by more efficient place and route algorithms, improved multiprocessor support, and faster timing-driven synthesis.
Quartus II Software Version 9.1 Features
- Rapid Recompile for Faster Design Iteration
The new Rapid Recompile further minimize design compilation times. Rapid Recompile maximizes designer productivity when making small engineering change order (ECO)-style design changes after a full compile is run, reducing compilation times by 50% on average versus running another full compile on the design. Rapid Recompile also significantly improves designer productivity during timing closure by preserving critical timing during late design changes.
- Expanded Device Support for New Cyclone IV FPGAs
The three smallest Cyclone IV GX devices will be supported in the Quartus II design software v9.1 with the remaining Cyclone IV devices supported in the Quartus II design software v9.1 service pack 1.
- Non-Rectangular Partitions with Incremental Compile
Non-rectangular regions help users create more compact and efficient floorplans, making it easier to achieve quality metrics. This new feature provides users a simpler and easier interface for finer control during design partitioning.
- Expanded SSN Analyzer Tool
With new support for Arria II GX FPGAs and Stratix IV GX FPGAs, this tool provides feedback on potential simultaneous switching noise (SSN) violations during pin assignments.
- New and Expanded IP Base Suite
Three new memory controllers supporting RLDRAM II, QDRII / II+ and DDR1/2/3 increase the suite to 14 intellectual property (IP) cores.
- Initial Support for VHDL 2008
Quartus II software maintains its leadership in language support by providing a more flexible language structure that allows users to create reusable code structures.
- Nios II Processor
The “/e” variant of the Nios II soft processor is now available without a license fee. This release also marks the debut of the Nios II software build tools for Eclipse, which provides improved software-development productivity.
- Expanded OS Support
Support for Linux SUSE 10 is now available.
More info: Altera