Vitesse 40G and 100G CI-BCH eFEC for ASIC and FPGA Implementation

Vitesse Semiconductor introduced their patented Continuously Interleaved BCH (CI-BCH) enhanced forward error correction (eFEC) technology for implementation in ASICs or FPGAs. According to Vitesse, their CI-BCH eFEC code offers the highest performing hard decision eFEC available and is the industry’s only eFEC implementable in FPGA form at 100G. Vitesse’s CI-BCH eFEC enables both 40G and 100G backbones to operate over 25% to 50% longer spans, respectively, with low power, low cost, and low latency.

Vitesse’s Continuously Interleaved BCH code is available for both FPGAs and ASICs. The CI-BCH code is offered at 7% and 20% FEC overhead for 40G and 100G implementations, respectively. The 7% overhead version offers 9.35 dB net electrical coding gain (NECG). The 20% version provides up to 10.5 dB NECG. The CI version of a class of base codes called BCH represents a unique advance in FEC codes, with superior performance to any block codes offered to date.

Vitesse 40G CI-BCH-3 eFEC Encoder/Decoder Core Specifications

Vitesse Semiconductor 40G CI-BCH-3™ eFEC Encoder/Decoder Core

  • Continuously Interleaved concatenated BCH (1020, 988) code
  • Capable of detecting up to 4 errors and correcting up to 3 errors
  • Can correct a burst of up to 1500 consecutive errors
  • <1 ~ 10-16 BER flaring floor with input BER of 4.4 ~ 10-3
  • Encoder Latency: <10,000 bits (0.25 µs at 40G)
  • Decoder Latency: ~1,000,000 bits (25 µs at 40G)
  • Interleave and number of iterations can be varied to reduce latency at expense of NECG performance

Vitesse 100G CI-BCH eFEC Codec Core Specifications

Vitesse Semiconductor 100G CI-BCH-3 eFEC Encoder/Decoder Core

  • Continuously interleaved concatenated BCH (1020, 988) code
  • Capable of detecting up to 4 errors and correcting up to 3 errors
  • Can correct a burst of up to 1500 consecutive errors
  • <1 ~ 10-16 BER flaring floor with input BER of 4.4 ~ 10-3
  • Encoder latency: <10,000 bits (0.1 µs at 100G)
  • Decoder latency: ~1,000,000 bits (10 µs at 100G)
  • Interleave and number of iterations can be varied to reduce latency at expense of NECG performance

More info: Vitesse Semiconductor