Xilinx Targeted Reference Designs Pass PCI-SIG Compliance Testing

During a recent PCI-SIG Compliance Workshop, Xilinx’s Spartan-6 FPGA Connectivity Targeted Reference Design passed the PCI-SIG compliance and interoperability testing for PCIe 1.1 single-lane configuration with on-chip GTP serial transceivers running at 2.5 Gbps. The Virtex-6 FPGA Connectivity Targeted Reference Design passed PCI-SIG compliance and interoperability testing for PCIe 2.0 x4-lane Gen2 configuration with the GTX Serial transceivers running at 5 Gbps. The Spartan-6 FPGA and Virtex-6 FPGA Connectivity Targeted Design Platforms are designed to provide out-of-the-box working PCIe connectivity solutions to enable designers to quickly connect and focus on the rest of the system.

Both Targeted Reference Designs provide designers with a high-performance platform for advanced Serial I/O design for use in applications such as wired communications systems, wireless infrastructure, audio, video, broadcast, industrial, automotive infotainment, aerospace, defense and high-end consumer devices.

The PCIe DMA-Gigabit Ethernet targeted reference design is integrated and included with the Xilinx Spartan-6 FPGA Connectivity Kit for $1,995. The PCIe 10G DMA-XAUI targeted reference design is integrated and included with the Xilinx Virtex-6 FPGA Connectivity Kit for $2,995.

Virtex-6 FPGA Connectivity Kit
The Virtex-6 FPGA Connectivity Kit is a fully validated and supported Connectivity Targeted Reference Design Framework that integrates built-in blocks for GTX transceivers and PCI Express, soft IP for XAUI protocol, a high-performance 10G DMA IP core from Northwest Logic and a Virtual FIFO memory controller interfacing to an external DDR3 memory. The Targeted Reference Design Framework includes hardware design and RTL source files, simulation environment, implementation scripts, design flows, Linux device drivers, and a GUI based software application.

Spartan-6 FPGA Connectivity Kit
The Spartan-6 FPGA Connectivity Kit is a fully tested and supported Connectivity Targeted Reference Design that integrates built-in blocks for PCI Express and Memory Controller, soft IP for Gigabit Ethernet and the DMA IP core from Northwest Logic. The Targeted Reference Design is a framework that features hardware design and RTL source files, simulation environment, implementation scripts and design flows, software device drivers, an application, and a GUI.

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