Synplicity, a business unit of Synopsys, Inc. (NASDAQ: SNPS), announced new products and enhanced capabilities to its field-programmable gate array (FPGA) implementation offering, Confirma ASIC/ASSP verification platform, and DSP synthesis products. The newest release of the Synplify Premier software features a number of new features — including graph-based physical synthesis for Altera’s Stratix devices, Synopsys Native SDC constraint support, and additional SystemVerilog language support. Synplify Premier 9.4 offers new technologies to address key challenges that FPGA designers face. These include timing closure, debug, IP integration, and system-level design. The Synplify Premier software’s graph-based physical synthesis technology addresses timing closure by generating timing estimates that are tightly matched to post-place-and-route results. The Synplify Premier software’s RTL instrumentation and Identify debugger technology provides an RTL debug environment within operating FPGAs. Synplify Premier also includes a system-level assembly and configuration tool to allow evaluation and integration of intellectual property (IP) in the ReadyIP program.
New additions to the Confirma verification platformare the HAPS-51T and HAPS-A31 ASIC prototyping systems. The HAPS-A31 is a single-FPGA motherboard equipped with Altera’s Stratix- III EP3SL340 FPGA in an F1760 package. It is the first HAPS board to use an Altera device and the first to adopt the PCI Express format, which permits the board to be plugged into a PC chassis as well as used on a lab bench. Target applications for the new HAPS-A31 include ASIC prototyping and FPGA- based accelerated computation (hardware-in-the-loop). Other enhancements to the Confirma platform include increased productivity and reliability for the Certify multi-FPGA implementation and partitioning tool. These benefits include: enhanced auto-partitioning providing designers an easy and automatic path to prototyping; a bottom-up netlist partition flow for significantly shorter runtime and fast incremental changes; and model-based area estimation, allowing designers to handle large designs efficiently.
The Identify Pro full-visibility debug tool with TotalRecall technology equips ASIC verification engineers using FPGA-based prototypes with a fast, powerful and productive debug methodology. Identify Pro provides full visibility into the design under test running at hardware speeds while at the same time enabling design debug at RTL source-code level using a standard RTL simulator such as the VCS simulation tool. Productivity-boosting capabilities include:
- Standard simulator integration (NC-Sim, VCS)
- Block-level full visibility debug
- Assertion triggering
- Mixed-language support
- ASIC design style support (gated clock, black-box, etc.)Innovative DSP Synthesis Methodology Yields More Accurate Results for FPGA and ASIC Designs
The newest version of the Synplify DSP synthesis tool has been enhanced with improved ASIC prototyping capabilities that offer significant benefits for both algorithm and verification teams working on wireless and digital multimedia ICs. These benefits include:
- A unified modeling and simulation environment that reduces the floating-point to fixed-point translation in MATLAB and verification. System engineering teams can quickly create detailed specification in the form of a “golden” high-level model.
- Automatic synthesis of cycle and bit-accurate RTL to implementation and verification flows that are consistent across different architectural optimizations needed for FPGA prototypes and final ASIC implementation.
- Integrated high-level DSP building blocks optimized for both FPGA and ASIC implementation.
- Greatly improved collaboration between the system and hardware verification teams.
- Integration with HAPS platforms to provide integrated and simple algorithm prototyping solutions.
More info: Synopsys