Compression and Encryption IP Cores for LatticeECP3 FPGA

Lattice Semiconductor and Helion Technology teamed on a family of compression and encryption IP cores for the LatticeECP3 FPGA devices. The new portfolio consists of the Payload Compression System core, LZRW lossless compression core, Fast Hash core, and Modular Exponentiation core. The compression and encryption IP cores for the LatticeECP3 FPGA are available now.

LatticeECP3 FPGA Compression and Encryption IP Core Family

  • Payload Compression System core
    • Enables improved utilization of constrained channel bandwidth
    • Seamlessly scalable from 500Mbps to over 3Gbps
    • Supports Layer 2 or Layer 3 for networking applications
    • Uses a very robust and mature implementation of the LZRW lossless compression algorithm
    • Ideal for microwave backhaul applications, broadband wireless access for 802.16e (WiMAX), and other Multi-Link Multi-In Multi-Out (MIMO) applications
  • LZRW lossless compression core
    • Available in Compress only, Expand only, or combined Compress/Expand versions
    • Supports data rates over 500Mbps
    • Ideal for applications more suited to embedded implementations
  • Fast Hash core family
    • Implements the NIST-approved SHA-1, SHA-256, SHA-384 and SHA-512 secure hash algorithms
    • FIPS 180-3 compliant
    • Legacy MD5 hash algorithm compliant to RFC1321
    • Available in single or dual-mode versions
    • Designed specifically for use with LatticeECP3 FPGAs
    • Super compact “Tiny” Hash core with full multi-mode support is also available
  • Modular Exponentiation core
    • For accelerating public/private key protocols
    • Easy to use and highly scalable solution
    • Available in several versions, each sharing an identical interface but differing in the number of clock cycles required to perform each operation

More info: Helion Technology | Lattice Semiconductor