Lattice ispLEVER v7.2 FPGA Design Tool Suite

Lattice Semiconductor Corporation (NASDAQ: LSCC) introduced version 7.2 of its ispLEVER® FPGA design tool suite with advanced place and route algorithms that deliver higher performance results in as much as 30% less time. The ispLEVER 7.2 software also now supports Lattice’s “clock boosting” flow for the LatticeECP2[tm] and LatticeECP2M[tm] FPGA families. Clock boosting can result in up to a 5% increase in FMax with no additional user input. Lattice’s ispLEVER 7.2 for Windows, Linux and UNIX users is available immediately without charge for customers with active design tool maintenance. The full ispLEVER design tool suite is priced at $1295 for the Windows version.

In addition to performance improvements, ispLEVER Version 7.2 continues to improve designers’ productivity with additional control, analysis and workflow enhancements, and includes the latest release of Synopsys’ Synplify Pro® advanced FPGA synthesis solution.

With new place and route techniques, ispLEVER software can now analyze a design and automatically choose the most appropriate algorithm for the design’s topology. For example, in a design with a connectivity pattern that is more likely to lead to routing congestion, the tool will automatically choose an algorithm that is appropriate to find better results in less time. In some cases the chosen algorithm can reduce runtime as much as 30%.

Properly constrained clock domains and cross-domain datapaths are critical to closing timing in today’s multi-clock designs. The Trace static timing analysis report now includes a “clock domain analysis” section. This is very useful for understanding the nature of the clock domains in the design, how they are currently constrained, where there are gaps in the constraint set and the datapaths that exist between the clock domains. In addition, the ispLEVER 7.2 tool suite gives more user control over the use of Global Set/Reset routing. This can result in improved routability and performance for designs with demanding routing requirements.

Also in this release, messages issued by the software’s Project Navigator may be traced through a mouse click directly to the related line of source text opened in the user’s favorite editor. Finally, source files may be imported using a list file, which eases the sharing of files between design tools.

More info: Lattice Semiconductor