Silicon Image CineramIC 4K and 3D H.264 Digital Video Decoder IP Core

Silicon Image introduced the cineramIC 4K and 3D H.264 digital video decoder IP core. With its high performance, low cost and high-quality video imaging, the cineramIC IP core can be integrated into System-on-Chips (SoCs) for next-generation digital TV (DTV), set-top-box (STB) and camcorder applications, as well as professional video editing, broadcast, medical, and surveillance FPGA applications.

Silicon Image CineramIC IP Core Features

  • Performance of up to 4K x 2K at 30 frames per second or high-definition 1080p 3D at 60 frames per second utilizing a single video pipeline implementation
  • Support for H.264, MPEG-1/2 and VC-1 decoding
  • Fully automatic multi-stream decoding for up to 16 streams, error detection and concealment, with very low software processing requirements
  • H.264 Multiview Video Coding (MVC) extension support for multi-camera 3D, surveillance and sports viewing applications
  • JPEG decoding of images up to 16K x 8K size with a decoding rate of 9 pictures per second for 32 Megapixel pictures

The cineramIC technology is designed to support HD, 3D, 4K, and higher resolution video decoding functions. A 4K (4K x 2K) resolution digital video decoder SoC using the cineramIC IP core running at 30 frames per second will require about 970k ASIC gates to implement with a minimum clock speed of only 300MHz. This implementation can decode compressed video streams of up to 160 mega bits per second (maximum average CABAC performance), with the ability to decode even the most difficult professional video streams.

FPGA implementations will use a lower clock speed and require additional gates to implement. Fewer than 2 million instructions per second (MIPS) of CPU time is required to decode 4K video streams, making the cineramIC IP core one of the industry’s highest performing, most efficient video decoders in the world. Similar hardware and software resources are required for decoding high-definition 1080p 3D 60 frames per second video content.

Silicon Image’s cineramIC IP core also supports multi-channel video decoding, including the latest H.264 Multiview Video Coding (MVC) extension. Up to 16 video streams can be automatically decoded without software intervention, reducing implementation complexity and improving time-to-market for 3D, surveillance and broadcast applications.

More info: Silicon Image