Altera and TSMC teamed on a heterogeneous 3D IC test vehicle. The process uses TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) integration process. Altera is the first semiconductor company to develop and complete characterization of a heterogeneous test vehicle using TSMC’s CoWoS process. This and additional test vehicles enable Altera to quickly test the capabilities and reliability of 3D ICs to ensure they meet yield and performance targets.
Heterogeneous 3D ICs are one of the innovations enabling the industry’s move beyond Moore’s Law. With 3D IC’s, multiple technologies can be stacked within a single device, including analog, logic and memory. TSMC’s integrated CoWoS process provides semiconductor companies developing 3D ICs an end-to-end solution that includes the front-end manufacturing process as well as back-end assembly and test solutions.
Altera plans to device derivatives that enables engineers to mix and match silicon IP based on application requirements. Altera will integrate various technologies with a FPGA, including CPUs, ASICs, ASSPs, memory and optics. Altera’s 3D ICs helps designers to differentiate their applications by leveraging the flexibility of the FPGA, while maximizing system performance, minimizing system power and reducing form factor and system cost.
CoWoS is an integrated process technology that attaches device silicon chips to a wafer through a chip on wafer (CoW) bonding process. The CoW chip is attached to the substrate (CoW-On-Substrate) to form the final component. By attaching the device silicon to the original thick wafer silicon before it finishes the fabrication process, manufacturing-induced warping is avoided. TSMC plans to offer CoWoS as a turnkey manufacturing service.