V1 ColdFire IP Core for Altera Cyclone III
IPextreme®, Inc. introduced the V1 ColdFire® IP core, which is optimized for Altera Cyclone III devices. The V1 ColdFire FPGA CIII Processor core can be downloaded, free of charge to Altera customers, at IPextreme’s Core Store. IPextreme will directly license and support the V1 ColdFire core to Altera customers.
The V1 ColdFire Processor offers a low-cost entry point into the ColdFire 32-bit processor architecture. A simplified version of the V2 ColdFire Processor, the V1 ColdFire Processor is a high performance low-power, low-area implementation that is fully upward compatible to other ColdFire implementations such V2, V3, and V4. Debug support is implemented through a single-wire background debug module (BDM) interface. A separate debug clock enables shut-down of debug logic when not in use.
V1 ColdFire Core Features
- 32-bit processor core with 24-bit address bus (upper 8 bits of 32-bit Avalon address bus are 0×00)
- Unified instruction/data bus
- Variable-length RISC architecture with 16-bit, 32-bit, and 48-bit instructions
- Independent, decoupled pipelines
- 2-stage Instruction Fetch Pipeline (IFP)
- 2-stage Operand Execution Pipeline (OEP)
- FIFO Instruction Buffer is the decoupling mechanism
- ColdFire Instruction Set Architecture Rev. C (ISA_C)
- Variable-length RISC architecture with 16-bit, 32-bit, and 48-bit instructions
- Standard ColdFire user programming model with 16 general-purpose, 32-bit registers
- Simplified supervisor programming model supporting a supervisor stack pointer, vector base register, and CPU configuration register
- Static branch prediction mechanisms minimize change-of-flow execution time
- Execute engines include ALU and barrel shifter
- Programmable response upon detection of certain illegal opcodes and illegal addresses (processor exception or system reset)
- ColdFire Debug B+ functionality mapped into the single-pin background debug module (BDM) interface
- Real time debug (RTD) support, with 6 hardware breakpoints (four PC, one address, and one data) that can be configured into a 1- or 2-level trigger with a programmable response (processor halt or interrupt)
More information: IPextreme
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