CebaTech Inc. announced the availability of the GZIP family of CebaIP Cores(TM). The GZIP family provides comprehensive, standards-based, lossless data compression for use in storage and data networking ASICs and FPGAs. Integrating the GZIP family of IP cores onto storage and data networking integrated circuits (ICs) can greatly reduce the operational costs of storing and transmitting data by end users of these ICs. Designers can choose from a number of available configurations to meet their desired speed, compression efficiency, and area requirements.
The GZIP family of cores is based on CebaTech’s integrated CebaIP Platform(TM). The CebaIP platform provides a modular approach to offering IP cores, enabling design engineers to quickly and easily integrate each configuration into their ASICs or FPGAs.
The GZIP family is standards-based and conforms to the popular “deflate” standard as specified in RFC1951. File formats for both ZLIB and GZIP, as specified in RFC1950 and 1952, are also supported. Data rates range from 2Gb/s and scale to 8Gb/s while typical compression ratios for benchmark files sets are in the range of 2.5:1 to 3.5:1.
GZIP-based compression and decompression is available now for customer engagements, with general availability of the AES function in mid-2007. Pricing for single use licenses start at $150,000. Future configurations of the CebaIP Platform that include partial TPC/IP, VLAN, link aggregation, and large send offload (LSO) will be released later in 2007.