MEN Micro P699 XMC and P598 Conduction-cooled PMC

The P699 XMC and the P598 conduction-cooled PMC (ccPMC), from MEN Micro, are FPGA-based mezzanine cards based on MEN Micro’s USM (Universal Submodule) concept. The boards use one or more IP cores in an FPGA to help designers easily and quickly turn individual I/O requirements into production-ready products reducing design time and costs.The use of Cyclone FPGAs on the two new cards enables exceptional I/O combinations in a very small space for moderate volumes and at a low cost. The P699 XMC uses a Cyclone III FPGA with 24,624 LE (logic elements) and the P598 ccPMC features a Cyclone II with 33,216 LE. Pricing for a USM development kit starts at $2,993. Delivery is two weeks ARO.

MEN Micro P699 XMCP699 XMC Features

  • Main XMC for USM Universal Submodules
  • PCIe 2.5 Gbits/s
  • 1 USM slot
  • 1 FPGA 24,624 LE (for user-defined I/O and Nios® soft core)
  • 32 MB DDR2 SDRAM
  • 4 MB Flash
  • -10 to +70°C screened

MEN Micro P598 conduction-cooled PMCP598 Conduction-Cooled PMC Features

  • Main PMC for USM Universal Submodules
  • Conduction-cooled
  • 1 USM slot
  • 1 FPGA 33,216 LE (for user-defined I/O and Nios® soft core)
  • 32 MB DDR2 SDRAM
  • 2 MB Flash
  • -40 to +85°C with qualified components

Different IP cores allow users to change the functionality of either card without any hardware modifications to the main module. The corresponding line drivers are implemented on the individually designed USM submodule that plugs into the main XMC or ccPMC. Because they function independently of other electronic components, the IP cores provide trouble-free, long-term operation over the temperature range of -40 degrees Celsius to +85 degrees Celsius (-40 degrees Fahrenheit to +185 degrees Fahrenheit).

A Nios soft core processor, which features 32 MB of DDR2 SDRAM main memory and 2 MB (P598) or 4 MB (P699) Flash memory, is implemented on the FPGA providing local intelligence to the main module.

A USM development package includes a main PMC with a USM submodule, test hardware and an FPGA package with a Nios CPU, memory control, connection to the PMC, Avalon/Wishbone bridges and detailed documentation. The Wishbone Bus Maker tool from MEN is included for development of IP cores on the standard Wishbone bus. The Nios core and the development of IP cores on the Avalon bus require Altera’s Quartus II design environment including the SOPC builder.

More info: P699 XMC | P598 ccPMC