New Certify Multi-FPGA ASIC Prototyping Software and Identify RTL Debugger
Synopsys released the latest version of their Certify multi-FPGA ASIC prototyping software and Identify RTL Debugger. The new release of Identify and Certify FPGA software tools feature an improved flow, which results in higher productivity for users of Synopsys’ HAPS FPGA-based prototyping systems. It also ensure that engineers who build their own hardware prototypes can [...]
Alico Kinetic 3500 OMAP FPGA Sensor Development Kit
Alico Systems introduced the Kinetic 3500 OMAP FPGA Sensor Development Kit. The Alico Kinetic 3500 SDK is a turn-key embeddable sensor development kit based on open source LInux software and includes critical device drivers and sample code. The Kinetic 3500 kid is priced at $1,695 ($1,945 with GPS option). It is ideal for embedded industrial, [...]
Elma FPGA-based VPX-300 OpenVPX Development Platform
Elma Electronic announced their VPX-300 OpenVPX reference platform. The 3U VPX development platform features a Virtex-6 FPGA based front end processor (FEP) card and uses a 7-slot backplane profile per VITA 65 BKP3-CEN07-15.2.3-n. The front end FPGA cluster performs incoming digital signal processing coupled via fabric to a back end data cluster. The Elma VPX-300 [...]
Altera Quartus II Software Version 11.1
Altera rolled out version 11.1 of their Quartus II design software for CPLD, FPGA and HardCopy ASIC designs. Quartus II software version 11.1 includes expanded support for Altera’s 28nm FPGAs, including compilation support for Arria V and Cyclone V FPGAs and enhanced support for Stratix V FPGAs. Both the Subscription Edition and the free Web [...]
White Paper: High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs
Xilinx recently published a white paper about floating-point DSP algorithms. According to the technical paper, Xilinx System Generator for DSP enables the creation of custom precision datapaths for optimal area and power. The floating-point design flow generates an implementation that is bit- and cycle-accurate to the original simulation model. The title of the white paper [...]
Aldec Active-HDL v9.1 FPGA Design and Simulation Tool
Aldec launched verion 9.1 of the Active-HDL FPGA Design and Simulation solution. Active-HDL v9.1 features auto-complete technology built into the HDL Editor, language templates, phrase highlighting, enhanced level of automation, and new HDL code browser tool that can detect errors in the source code even before compilation. The HDL-based tool supports design creation and simulation [...]
Xilinx ISE Design Suite 13.3 Supports Full Custom Precision Floating-Point
Xilinx released version 13.3 of their ISE Design Suite for DSP designers. The latest version of the tool makes it easier to implement bit-accurate single, double and full custom precision floating-point math operations in designs for wireless, medical, aerospace and defense, high-performance computing and video applications. ISE Design Suite 13 is available now for all [...]
Zynq-7000 EPP Extensible Virtual Platform
Xilinx and Cadence Design Systems have developed an extensible virtual platform for Zynq-7000 Extensible Processing Platform (EPP) based systems. The virtual platform enables system design, software development, and testing prior to hardware availability. The Cadence/Xilinx solution can map the Zynq-7000 family’s extensibility without the need for any hardware other than a workstation. Early access to [...]
Imperas and OVP Model for Xilinx MicroBlaze Soft Processor Core
Imperas has developed a model of the Xilinx MicroBlaze soft processor core. With the help of Xilinx, Imperas successfully verified the OVP Fast Processor Model of the MicroBlaze. The OVP Fast Processor Model of the MicroBlaze soft processor core will be fully released by the end of year. The OVP Fast Processor Model and example [...]
Lattice IspLEVER Classic v1.5 Design Tool Suite
Lattice Semiconductor rolled out version 1.5 of their ispLEVER Classic design tool suite. The ispLEVER Classic 1.5 design software suite supports ispMACH 4000ZE CPLD family; GAL and ispGAL Simple PLDs (SPLDs); ispLSI, MACH, ispMACH and ispXPLD Complex PLDs (CPLDs); ORCA, FPSC and ispXPGA Field Programmable Gate Arrays (FPGAs); and ispGDX/ispGDX2 crosspoint devices. Lattice ispLEVER Classic [...]
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