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Synopsys Debuts Deep Trace Debug for HAPS FPGA-based Prototyping Systems

Ken Cheung — Thu, 26 Apr 2012 15:26:26 +0000

Synopsys rolled out a new Deep Trace Debug feature for their HAPS FPGA-based prototyping systems. HAPS Deep Trace Debug increases productivity for debugging complex SoCs by enabling prototypers to capture the long signal trace history needed to identify the root cause of design bugs. HAPS Deep Trace Debug support in Synopsys’ Identify RTL debugger software and HAPS Deep Trace Debug SRAM daughter boards is available now.

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Xilinx Introduces Display Targeted Design Platform for 4K2K Displays

Ken Cheung — Tue, 17 Apr 2012 15:53:36 +0000

Xilinx introduced the Display Targeted Design Platform. The Display TDP is based on the Tokyo Electron Device ACDC (acquisition, contribution, distribution and consumption) 1.0 hardware platform. The solution will enables engineers to quickly develop systems for 4K2K video. According to Xilinx, the TDP will make 4K2K displays as ubiquitous as 1080p flat screen monitors. The ACDC 1.0 baseboard with the Kintex-7 FPGA as well as the targeted reference designs will be available this quarter.

Altera, Eutecus Team on Four-Channel Video Analytics Solution

Ken Cheung — Mon, 16 Apr 2012 16:08:50 +0000

Altera introduced a new four-channel, standard definition (SD) video analytics solution targeting digital video recorders (DVRs) and network video recorders (NVRs) for surveillance systems. The four-channel D1 video analytics solution is available now. The FPGA-based video surveillance solution is ideal for banking, education, city, industrial, government and traffic surveillance systems. Altera’s latest video analytics solution was jointly developed with Eutecus.

Synopsys Synplify FPGA Synthesis Tools v2012.03 Reduce Runtime by 30%

Ken Cheung — Mon, 02 Apr 2012 15:54:15 +0000

Synopsys launched version 2012.03 of their Synplify Pro and Synplify Premier FPGA synthesis tools. The new Synplify 2012.03 products include a new continue-on-error feature, hierarchical design techniques, and improved algorithms that deliver faster runtimes. The latest Synplify Pro and Synplify Premier synthesis software is available now. Customers with a current maintenance agreement can download the 2012.03 release from Synopsys using their SolvNet account. The Synplify FPGA synthesis products are supported on Windows and Linux, 32 and 64-bit platforms.

Synopsys, Altera, TSMC Team on Silicon-Accurate Parasitic Modeling and Extraction

Ken Cheung — Wed, 28 Mar 2012 16:17:20 +0000

Synopsys, Altera and TSMC teamed together to create silicon-accurate modeling of key parasitic effects in Synopsys’ StarRC solution for TSMC’s 28 nanometer (nm) processes. Altera has successfully deployed StarRC to achieve signoff accurate extraction and accelerate the design cycle of its 28nm FPGA designs. StarRC is now fully deployed as the signoff parasitic extraction solution for 28-nanometer Stratix V FPGA devices.

SynaptiCAD Improves VeriLogger Extreme Verilog Simulator

Ken Cheung — Fri, 23 Mar 2012 14:41:58 +0000

SynaptiCAD rolled out a new version of VeriLogger Extreme, which is a Verilog simulator. For a limited time, SynaptiCAD will give away free “no strings attached” six-month licenses for VeriLogger Extreme. Free licenses will be available for both Linux and Windows versions of the simulator. Unlike the lower cost simulators typically provided with FPGA tools, SynaptiCAD’s simulator is being distributed without any code that slows down the simulator when run on larger designs.

Blue Pearl Software Suite Supports Synopsys Synplify Pro FPGA Synthesis

Ken Cheung — Mon, 19 Mar 2012 16:14:08 +0000

Blue Pearl Software Suite now supports Synopsys’ Synplify Pro FPGA synthesis software for VHDL and SystemVerilog designs. Blue Pearl Software collaborated with Synopsys to create an optimized flow that works with Synplify Pro FPGA synthesis software. VHDL and SystemVerilog designers are now able to automatically generate an exhaustive set of constraints that address false and multi-cycle paths and that work with Synopsys’ synthesis flow.

Aldec Releases Riviera-PRO 2012.02 for FPGA and ASIC Verification

Ken Cheung — Tue, 13 Mar 2012 16:05:33 +0000

Aldec released version 2012.02 of their Riviera-PRO. The latest version of the mixed-language verification tool supports a number of advanced verification methodologies that will benefit the designers of complex FPGAs and those migrating to ASIC. Riviera-PRO v2012.02 supports the verification environments constructed with the Universal Verification Methodology (UVM) class library and new SystemVerilog IEEE 1800-2009 and VHDL IEEE 1076-2008 constructs. This makes Riviera-PRO an ideal platform for working with the Open Source VHDL Verification Methodology (OS-VVM).

Lattice HDR-60 Video Camera Development Kit Includes New Helion GUI

Ken Cheung — Mon, 12 Mar 2012 16:03:10 +0000

Lattice Semiconductor had upgraded their HDR-60 Video Camera Development Kit. The Lattice HDR-60 is now enhanced with a Helion Graphical User Interface (GUI). The new GUI makes the engineer’s job even easier. It offers ease-of-use while improving design accuracy, further enhancing the user experience. The enhanced HDR-60 GUI will be available for download next week at no additional charge to current and new customers of the Lattice HDR-60 Video Camera Development Kit.

MathWorks Launches HDL Coder and HDL Verifier HDL Code Generation Tools

Ken Cheung — Tue, 06 Mar 2012 17:44:51 +0000

MathWorks introduced HDL Coder and HDL Verifier. HDL Coder automatically generates HDL code from MATLAB and helps engineers implement FPGA and ASIC designs from the MATLAB language. HDL Verifier features FPGA hardware-in-the-loop capabilities for testing FPGA and ASIC designs. HDL Coder and HDL Verifier are available now. Pricing for HDL Verifier starts at $3,250 and pricing for HDL Coder starts at $10,000. With HDL Verifier and HDL Coder, MathWorks now provides HDL code generation and verification across their MATLAB and Simulink tools.