Lattice ispLEVER 7.1 FPGA Design Tool Suite
ispLEVER 7.1 is the latest FPGA design software from Lattice Semiconductor Corporation (NASDAQ: LSCC). The new tool release delivers a number of new functional and performance-enhancing features, including the industry's first dedicated FPGA Simultaneous Switching Output (SSO) Analyzer. The SSO Analyzer enables FPGA designers to actively analyze and optimize I/O pin placement and output switching […]
GiDEL Upgrades PROC_SoC Verification System
GiDEL released a new generation of their PROC_SoC[TM] Verification System. The PROC_SoC family is designed to debug and verify SoC designs of diverse design styles. The new generation has doubled the capacity of the system by incorporating Altera's new Stratix® III EP3SL340, the world's largest and fastest FPGA. PROC_SoC System delivery times are 4-6 weeks […]
Impulse C Compiler for Virtex-5 FXT FPGA
Impulse Accelerated Technologies Inc. announced that its Impulse C(tm) compiler fully supports Xilinx's just released Virtex(tm)-5 FXT field programmable gate arrays (FPGAs) with their available embedded PowerPC processor. Full support in the Impulse C-to-FPGA tools allows embedded systems designers to easily create hardware-accelerated image processing, DSP and other applications, using the Virtex-5 FXT's embedded PowerPC® […]
Aldec DO-254 Compliance Tool Set for Altera Devices
Aldec, Inc. announced a comprehensive in-hardware verification solution that supports Altera Corporation (NASDAQ: ALTR) customers with DO-254 compliance projects. The global partnership combines Altera's FPGA and HardCopy ASIC devices with Aldec's DO-254 Compliance Tool Set (CTS), creating an in-hardware verification solution addressing Level A and Level B compliance requirements of the RTCA DO-254 specification.
Aldec provides […]
DO-254 Global Partner Network
Altera Corporation (NASDAQ:ALTR) launched the DO-254 Global Partner Network. Altera, Aldec, Geensys, HighRely, and HCELL Engineering provide a comprehensive environment of DO-254-certifiable intellectual property (IP) cores, in-hardware verification flows and documentation. The inaugural partners provide specialty solutions and services that enable Altera® FPGA and HardCopy® ASIC solutions to be quickly approved and implemented in avionics […]
Aldec Hardware Emulation System 2008.03
Aldec Incorporated released HES(tm) (Hardware Emulation System) 2008.03. The latest release of HES expands the functionality of commercial prototyping boards from The DINI Group and Synopsys®/Synplicity® HAPS(tm) to enable RTL simulation acceleration and emulation on ASIC designs up to 31 million gates. Both design and verification engineers can now benefit from verifying ASIC designs in […]
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