Synopsys Debuts Deep Trace Debug for HAPS FPGA-based Prototyping Systems
Synopsys rolled out a new Deep Trace Debug feature for their HAPS FPGA-based prototyping systems. HAPS Deep Trace Debug increases productivity for debugging complex SoCs by enabling prototypers to capture the long signal trace history needed to identify the root cause of design bugs. HAPS Deep Trace Debug support in Synopsys’ Identify RTL debugger software [...]
Xilinx Introduces Display Targeted Design Platform for 4K2K Displays
Xilinx introduced the Display Targeted Design Platform. The Display TDP is based on the Tokyo Electron Device ACDC (acquisition, contribution, distribution and consumption) 1.0 hardware platform. The solution will enables engineers to quickly develop systems for 4K2K video. According to Xilinx, the TDP will make 4K2K displays as ubiquitous as 1080p flat screen monitors. The [...]
Altera, Eutecus Team on Four-Channel Video Analytics Solution
Altera introduced a new four-channel, standard definition (SD) video analytics solution targeting digital video recorders (DVRs) and network video recorders (NVRs) for surveillance systems. The four-channel D1 video analytics solution is available now. The FPGA-based video surveillance solution is ideal for banking, education, city, industrial, government and traffic surveillance systems. Altera’s latest video analytics solution [...]
Synopsys Synplify FPGA Synthesis Tools v2012.03 Reduce Runtime by 30%
Synopsys launched version 2012.03 of their Synplify Pro and Synplify Premier FPGA synthesis tools. The new Synplify 2012.03 products include a new continue-on-error feature, hierarchical design techniques, and improved algorithms that deliver faster runtimes. The latest Synplify Pro and Synplify Premier synthesis software is available now. Customers with a current maintenance agreement can download the [...]
Synopsys, Altera, TSMC Team on Silicon-Accurate Parasitic Modeling and Extraction
Synopsys, Altera and TSMC teamed together to create silicon-accurate modeling of key parasitic effects in Synopsys’ StarRC solution for TSMC’s 28 nanometer (nm) processes. Altera has successfully deployed StarRC to achieve signoff accurate extraction and accelerate the design cycle of its 28nm FPGA designs. StarRC is now fully deployed as the signoff parasitic extraction solution [...]
SynaptiCAD Improves VeriLogger Extreme Verilog Simulator
SynaptiCAD rolled out a new version of VeriLogger Extreme, which is a Verilog simulator. For a limited time, SynaptiCAD will give away free “no strings attached” six-month licenses for VeriLogger Extreme. Free licenses will be available for both Linux and Windows versions of the simulator. Unlike the lower cost simulators typically provided with FPGA tools, [...]
Blue Pearl Software Suite Supports Synopsys Synplify Pro FPGA Synthesis
Blue Pearl Software Suite now supports Synopsys’ Synplify Pro FPGA synthesis software for VHDL and SystemVerilog designs. Blue Pearl Software collaborated with Synopsys to create an optimized flow that works with Synplify Pro FPGA synthesis software. VHDL and SystemVerilog designers are now able to automatically generate an exhaustive set of constraints that address false and [...]
Aldec Releases Riviera-PRO 2012.02 for FPGA and ASIC Verification
Aldec released version 2012.02 of their Riviera-PRO. The latest version of the mixed-language verification tool supports a number of advanced verification methodologies that will benefit the designers of complex FPGAs and those migrating to ASIC. Riviera-PRO v2012.02 supports the verification environments constructed with the Universal Verification Methodology (UVM) class library and new SystemVerilog IEEE 1800-2009 [...]
Lattice HDR-60 Video Camera Development Kit Includes New Helion GUI
Lattice Semiconductor had upgraded their HDR-60 Video Camera Development Kit. The Lattice HDR-60 is now enhanced with a Helion Graphical User Interface (GUI). The new GUI makes the engineer’s job even easier. It offers ease-of-use while improving design accuracy, further enhancing the user experience. The enhanced HDR-60 GUI will be available for download next week [...]
MathWorks Launches HDL Coder and HDL Verifier HDL Code Generation Tools
MathWorks introduced HDL Coder and HDL Verifier. HDL Coder automatically generates HDL code from MATLAB and helps engineers implement FPGA and ASIC designs from the MATLAB language. HDL Verifier features FPGA hardware-in-the-loop capabilities for testing FPGA and ASIC designs. HDL Coder and HDL Verifier are available now. Pricing for HDL Verifier starts at $3,250 and [...]
If you are familiar with RSS feeds, you can also sign up for our free blog feed. Our RSS feed is updated in real-time while our newsletter is updated daily.
