Industrial Ethernet IP Cores for Altera FPGA
Altera (NASDAQ: ALTR) announced intellectual property (IP) cores for Ethernet communications protocols used in industrial automation applications can now be implemented on Altera’s low-cost Cyclone(R) series FPGAs. The protocols supported include ProfiNet, Ethernet/IP, Modbus-IDA, EtherCAT, SERCOS III Interface, and Ethernet Powerlink.
The Industrial Ethernet IP cores enable designers to implement any of the standards on a [...]
Lattice Validates TOPPERS with LatticeMico32
Lattice Semiconductor Corporation (NASDAQ: LSCC) validated the operation of the TOPPERS open source implementation of the mITRON 4.0 Real Time Operating System (RTOS) with its LatticeMico32(TM) 32-Bit soft microprocessor. This expands the RTOS options available to users of the LatticeMico32 microprocessor, and is particularly significant because mITRON represents the de facto RTOS for embedded applications [...]
Lattice Supports HyperTransport, Releases Reference Design
Lattice Semiconductor (NASDAQ: LSCC) recently announced HyperTransport(TM) support and the release of the PURESPEED I/O Alignment Reference Design.
The LatticeSC(TM) and LatticeSCM(TM) FPGA families (LatticeSC/M families) now support HyperTransport technology at rates up to 1600Mbps, QDRII+ rates up to 750Mbps, RLDRAM(R) II rates of 800Mbps and DDR2 interface speeds of 667Mbps. HyperTransport technology and the memory [...]
Xilinx in the News - 2007.04.17
Deserializer Reference Design
Xilinx announced immediate availability of a Virtex-4 FPGA-based deserializer reference design, application note and evaluation module jointly developed with Texas Instruments. The new reference design, together with the accompanying application note, deserializes data streams from TI’s ADS6000 analog-to-digital converter (ADC) family, providing designers a quick and easy solution with which to deploy products [...]
PURESPEED Burst Mode Receiver FPGA Reference Design
Lattice’s PURESPEED is an I/O burst mode receiver FPGA reference design for gigabit passive optical networks. The reference design uses Lattice’s Adaptive Input Logic (AIL) block to rapidly establish stable clock to data timing relationships within the fast lock times specified in the GPON ITU-T G.984.1 specification, which requires the Optical Line Termination (OLT) to [...]
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