'Reference Design' Category Archive

Xilinx Attends International Broadcasting Convention 2007

Posted by Ken Cheung in Event, FPGA, IP Core, Reference Design on Friday, September 7, 2007

Xilinx (Nasdaq: XLNX) made several announcements at the International Broadcasting Convention (IBC) in Amsterdam:
Xilinx, MindWay Announce Digital Television Modulation IP Cores
Xilinx, Inc. (Nasdaq: XLNX), the world's leading provider of programmable logic solutions, and MindWay S.r.l., an IP core and design services company, announced availability of new digital television modulation IP cores based on Xilinx(R) Virtex(TM)-5 [...]

Altera's High Definition Quality Initiative

Posted by Ken Cheung in IP Core, Reference Design on Thursday, September 6, 2007

Altera (Nasdaq: ALTR) announced their High Definition Quality Initiative (HDQI) today. The initiative's objective is to enable designers to quickly and cost-effectively address the rapidly growing need for high-quality HD systems. HDQI is backed by partners with expertise in the HD space. 4i2i, ATEME, Let It Wave, and PLDA are among the initiative's founding members.
The [...]

Xilinx 400 Mbps DDR2 SDRAM Interface Reference Design

Posted by Ken Cheung in Reference Design on Tuesday, August 7, 2007

Xilinx (NASDAQ:XLNX) announced support for a 400 Mbps DDR2 SDRAM interface (DDR2-400) with its low-cost 90 nm Spartan(TM)-3A and Spartan(TM)-3AN FPGAs. Designers can download a free hardware verified reference design providing quick implementation of a 400 Mbps DDR2 SDRAM interface. DDR2 SDRAM interfaces are widely used in applications such as low-cost video and networking.
The 400 [...]

Actel System Management Reference Design

Posted by Ken Cheung in Reference Design on Monday, August 6, 2007

Actel (NASDAQ: ACTL) is offering a new system management reference design for $1.20 . The design combines a mixed-signal Fusion Programmable System Chip (PSC) with an optimized, configurable CoreABC microcontroller to provide a complete system management solution using a fraction of the Fusion part's logic tiles. As a result, the small and flexible design eliminates [...]

Xilinx Virtex-5 FPGA Interoperates with DDR3 SDRAM

Posted by Ken Cheung in FPGA, Reference Design, Tool on Tuesday, July 31, 2007

Xilinx (NASDAQ: XLNX) announced that its Virtex(TM)-5 FPGA devices are interoperable with 800 Mbps DDR3 SDRAM devices from leading memory suppliers. Hardware-proven interoperability with Virtex-5 devices provides customers with an early path to adopt DDR3 SDRAM technology with the industry's only high-performance 65-nm FPGA family shipping in production.
Successful interoperability hardware tests were performed using devices [...]

Industrial Ethernet IP Cores for Altera FPGA

Posted by Ken Cheung in IP Core, Reference Design on Wednesday, July 25, 2007

Altera (NASDAQ: ALTR) announced intellectual property (IP) cores for Ethernet communications protocols used in industrial automation applications can now be implemented on Altera's low-cost Cyclone(R) series FPGAs. The protocols supported include ProfiNet, Ethernet/IP, Modbus-IDA, EtherCAT, SERCOS III Interface, and Ethernet Powerlink.
The Industrial Ethernet IP cores enable designers to implement any of the standards on a [...]

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