FPGA Blog » Reference Design

Maxim 1-Wire Security Reference Design Protects Spartan-6 FPGA-Based Designs

Ken Cheung — Mon, 30 Apr 2012 15:36:15 +0000

Maxim Integrated Products introduced a reference design that will protect Xilinx Spartan-6 field-programmable gate arrays (FPGAs). The reference design features security software (from Maxim or Xilinx) and the Maxim DS28E01-100 1-Wire secure memory device. Engineers can easily add a level of design security to products with the Maxim DS28E01-100 1-Wire secure memory device. In the future, the reference design will support Artix-7, Kintex-7, Virtex-7 and the Zynq-7000 FPGA devices.

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Microsemi Introduces SmartFusion LCD Display Reference Design

Ken Cheung — Wed, 18 Apr 2012 15:42:29 +0000

Microsemi recently introduced a LCD display reference design for industrial and medical applications. The reference design is based on the SmartFusion customizable system-on-chip. The SmartFusion cSoC integrates FPGA technology with a hardened ARM Cortex-M3 processor and programmable analog blocks. The SmartFusion display reference design source files and user’s guide are available now.

Lattice Semiconductor Introduces Sony IMX136 Image Sensor Bridge

Ken Cheung — Mon, 26 Mar 2012 15:47:47 +0000

Lattice Semiconductor introduced the Sony IMX136 image sensor bridge. The new image sensor bridge design utilizes the low power, low cost Lattice MachXO2 PLD (programmable logic device) to interface to the Sony IMX136 image sensor. The Sony IMX136 image sensor bridge design helps engineers to quickly introduce cameras based on the Sony IMX136. The image sensor bridge design is available now for download, and the MachXO2-1200 PLD is in full production.

Lattice Semiconductor, Aptina Team on Dual Image Sensor Stereo Camera Reference Design

Ken Cheung — Fri, 06 Jan 2012 15:43:47 +0000

Lattice Semiconductor and Aptina will showcase a low cost, dual image sensor design at the Consumer Electronics Show (CES) in Las Vegas, January 10-13, 2012. The dual image sensor design helps ISP vendors to quickly offer multiple camera solutions for the consumer market. Lattice’s private hospitality meeting suite will be held in the Las Vegas Hilton, North Hall, 28th Floor, Suite 127.

Xilinx Targets 3D and 4K2K Displays with Reference Designs and ACDC Baseboard

Ken Cheung — Thu, 05 Jan 2012 16:46:14 +0000

Xilinx introduced reference designs and a development baseboard for speeding the development of next-generation, 3D and 4K2K display technologies. The 4K2K Mosaic and HDTV-to-4K2K up-converter targeted reference designs are based on the new 28nm Kintex-7 Field Programmable Gate Array (FPGA). The new ACDC (Acquisition, Contribution, Distribution and Consumption) 1.0 Baseboard also uses Kintex-7 FPGA devices. The targeted reference designs and ACDC 1.0 Baseboard with the Kintex-7 FPGA will be available in Q2 2012.

Valens HDBaseT Camera Reference Design

Ken Cheung — Mon, 31 Oct 2011 15:38:58 +0000

Valens Semiconductor introduced a HDBaseT camera reference design solution. The LatticeECP3 FPGA device can be used for multiplexing the video streams and formatting the data to the Valens HDBaseT Tx driver. The LatticeECP3 FPGA device has the necessary memory blocks, FPGA logic, SERDES and configurable I/O to implement a variety of applications. The LatticeECP3 FPGA gives manufacturers the flexibility to adapt and format interfaces to leverage the Valens HDBaseT bandwidth capability.

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Xilinx Acquires Modelware, Debuts 100G Traffic Management Reference Design

Ken Cheung — Mon, 09 May 2011 16:56:46 +0000

Xilinx has acquired Modelware, which is a provider of traffic management/packet processing silicon intellectual property (IP) cores and reference designs that simplify system development and enable greater differentiation for networking applications supporting 10G, 40G, 100G and beyond. Xilinx also announced a FPGA-based 100G traffic management reference design for speeding evaluation and implementation of high bandwidth packet processing applications.

Xilinx Broadcast Real-Time Video Engine Targeted Design Platform

Ken Cheung — Mon, 11 Apr 2011 16:55:44 +0000

Xilinx introduced their Broadcast Real-Time Video Engine Targeted Design Platform. The Real-Time Video Engine Targeted Design Platform consists of a broadcast-quality Video and Image Processing IP pack. The Xilinx Video and Imaging Processing IP pack is priced at $3,000 and will be available at the end of April. Xilinx also rolled out the SMPTE2022 IP core, which helps engineers speed the development of hardware to process high quality video and deliver it at rates as high as 10 Gbps over Internet Protocol. The Xilinx core will be available in the fourth quarter of this year.

LatticeXP2 HiSPi to Parallel Sensor Bridge Reference Design

Ken Cheung — Mon, 04 Apr 2011 16:52:16 +0000

Lattice Semiconductor introduced a HiSPi bridge reference design that supports Aptina’s High-Speed Serial Pixel Interface. The reference design is based on LatticeXP2 FPGA devices, which can support four HiSPi data lanes up to 700Mpbs. The HiSPi bridge solution enables an Image Signal Processor (ISP) with a CMOS parallel bus to interface with an Aptina HiSPi CMOS sensor. The free reference design supports all modes of the Aptina HiSPi specification. The LatticeXP2 HiSPi bridge reference design is ideal for security cameras, automotive applications, and high end consumer cameras.

Xilinx Virtex-6 HXT FPGA Optical Transport Network Design Platform

Ken Cheung — Mon, 07 Mar 2011 22:20:16 +0000

Xilinx introduced the Virtex-6 HXT FPGA Optical Transport Network (OTN) Targeted Design Platform. The OTN Targeted Design Platform features a Virtex-6 HXT FPGA development board with pre-defined and implemented reference designs for different OTN solutions, such as 100G ODU switching from Xilinx, 100G Ethernet to OTU4 transponders and 10×10 to OTU4 transponders. The OTN platform also includes a highly optimized IP 100G MuxSAR solution developed by Omiino. The Virtex-6 HXT FPGA OTN Kit will be available in April for $25,000 (without optical modules).