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'Reference Design' Category Archive

3G, 4G Remote Radio Head Solution by Lattice Semiconductor, Affarii

Posted by Ken Cheung in Reference Design on Monday, October 26, 2009

Lattice Semiconductor and Affarii Technologies have developed a complete 3G/4G-based Remote Radio Head (RRH) solution for wireless infrastructure designers. This is the first time a full RRH solution has been made available using low power, low cost FPGAs that enables low power RRHs to be deployed without sacrificing flexibility or performance. The RRH solution is [...]

Lattice MachXO Control Development Kit

Posted by Ken Cheung in Reference Design, Tool on Monday, October 19, 2009

Lattice Semiconductor introduced the new MachXO Control Development Kit and 12 new reference designs for prototyping system control functions such as temperature and current monitoring, power supply sequencing, fan control and fault logging, that are commonly found in telecom infrastructure, server, industrial and medical applications. The MachXO kit enables the development of system control designs [...]

Reference Clock Solution for SERDES Applications

Posted by Ken Cheung in Reference Design on Monday, October 12, 2009

Lattice Semiconductor and Epson Toyocom teamed together on a low-cost reference clock solution for SERDES applications. The reference design features Lattice’s ispClock 5400D device and Epson Toyocom’s SG-710ECK CMOS oscillator. The 6-output ispClock5406D device is available for $2.95 in 10K piece volumes. The Epson Toyocom SG-710 is available for $0.95 in quantities of 10K piece [...]

Lattice Semiconductor ProcessorPM, ispMACH 4000ZE Pico Development Kits

Posted by Ken Cheung in Reference Design, Tool on Tuesday, September 8, 2009

Lattice Semiconductor introduced the ProcessorPM Development Kit, the ispMACH 4000ZE Pico Development Kit, and eight new reference designs. Pricing for the ispMACH 4000ZE Pico Development Kit is $69 and the ProcessorPM Development Kit is $49. The kits are ideal for prototyping high volume, cost sensitive, low power, space constrained applications. With Lattice’s low-cost programmable logic [...]

Achronix Speedster SPC60 Plug-In Card for SPD60 FPGA

Posted by Ken Cheung in Reference Design on Tuesday, August 4, 2009

Achronix Semiconductor introduced the Speedster SPC60 Plug-In Card for the Achronix SPD60 FPGA. The SPC60 development kit features a 1066 Mbps DDR3 reference design for out of the box integration with customer designs. The SPC60 embeds the 1066 Mbps DDR3 controllers in the SPD60 FPGA and eliminates difficult memory interface implementation and verification challenges. The [...]

Pigeon Point Board Management Reference

Posted by Ken Cheung in Reference Design on Tuesday, July 21, 2009

Pigeon Point Systems (PPS) updated their board management reference (BMR) starter kit for AdvancedTCA management controllers. The updated board management reference includes support for advanced in-shelf network attachment via the Network Controller Sideband Interface (NC-SI) standard. The NC-SI support is implemented in BMR solutions based on the Actel Fusion mixed-signal FPGA. These and corresponding solutions [...]

Actel Mixed-Signal Power Manager

Posted by Ken Cheung in Reference Design on Monday, July 13, 2009

The Mixed-Signal Power Manager (MPM), from Actel, is a reference design and graphical user interface (GUI) tool included in the Fusion Advanced Development Kit. MPM helps designers control and reduce power at the system level. It offers fully-verified, timing-closed, proven-in-hardware power supervision and management capabilities. Designers can configure power management sequencing, levels, or thresholds using [...]

Actel Design Examples for Low-Power FPGA Applications

Posted by Ken Cheung in Reference Design on Monday, May 4, 2009

Actel introduced eight free design examples for use with their low-power, flash-based FPGAs. The design examples are optimized for use with Actel’s low power ProASIC 3 FPGAs and IGLOO FPGAs, including the lowest power FPGAs in the industry, IGLOO nano. The design examples are specifically targeted at designs requiring a low-power companion solution for input/output [...]

Actel Display Reference Designs

Posted by Ken Cheung in Reference Design on Tuesday, April 28, 2009

Actel is offering five reference designs and VHDL source code free of charge. The reference designs enable the design and deployment of display applications quickly and effectively. The validated and tested reference designs are implemented using the IGLOO Video Demo Kit, which was jointly developed by Actel, Attodyne and Avnet Memec. The kit is available [...]

Actel Demonstrations at Embedded World

Posted by Ken Cheung in Event, Reference Design on Monday, March 2, 2009

At Embedded World, Actel will show how Actel low power FPGAs and mixed-signal FPGAs can integrate multiple functions and applications into a single device, offering maximum flexibility, faster time-to-market, and reduced power consumption.
Actel Demonstrations

FPGA-optimized ARM Cortex-M1 processor running on Actel Fusion mixed-signal FPGAs to show current, temperature and voltage monitoring and other intelligent system and [...]

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