Interactive reference tool “Pins” by Opal Kelly replaces PDF and text-based reference materials with browser-based tool aims to help usability and reduce errors.
CAST announced the H.264 Video Over IP – HD Encoder Subsystem. The reusable subsystem makes it easier to build video streaming into mobile and other products. Reference designs for the streaming subsystem are available now for the Altera Stratix IV and Arria V families, and the Xilinx Kintex-7 line. These include the CAST and other essential IP cores implemented in an FPGA, plus the necessary interfaces, memory, drivers, and software.
Analog Devices recently launched the JESD204B Xilinx Transceiver Debug Tool. The FPGA-based reference design with software and HDL code reduces the design risk of high-speed systems incorporating JESD204B-compatible converters. It supports the 312.5-Mbps to 12.5-Gbps JESD204B data converter-to-FPGA serial data interface and Xilinx Inc., 7 series FPGAs and Zynq-7000 All Programmable SoCs.
Barco Silex released the multi-channel Video over IP with JPEG 2000 reference design. The VoIP reference design integrates the BarcoSilex JPEG 2000 Encoder and Decoder IP Cores, the Barco Silex high-performance memory controller core, and the Xilinx SMPTE 2022-1/2 and Ethernet MAC LogiCORE IP Cores for Xilinx 7 Series FPGAs and Zynq All Programmable SoC.
Altera introduced a direct memory access (DMA) reference design. The solution is constructed for Stratix V customers needing to seamlessly and quickly design PCIe Gen3 solutions. Stratix V GX FPGAs feature a hardened protocol stack for PCIe Gen3 applications, demanding the highest in bandwidth, system integration and flexibility, at a reduced cost with lower total power consumption. The new DMA reference design makes it fast and easy to develop high-performance PCIe Gen3x8 hardware.
Lattice Semiconductor recently introduced the SensorExtender reference design. The Sensor Extender is a low-cost solution for remotely locating image sensors up to eight meters away from the image signal processor (ISP) and transmit and receive video signals at resolutions that range up to 720p60 and 1080p30. The reference design is tested with the Aptina MT MT9M024 and the Lattice HDR-60 camera development kit’s base board.
Xilinx released version 2.1 of their Real-Time Video Engine. RTVE runs on the OZ745 Zynq-7045 All Programmable system-on-a-chip (SoC) baseboard from OmniTek. RTVE 2.1 is a key component of the Xilinx All Programmable Smarter Vision solutions, which combines the Zynq-7000 All Programmable SoC, Vivado High-Level Synthesis (HLS) with IP integrator software tools, OpenCV libraries, SmartCORE IP and hardware development kits
Altera and Flexibilis developed a High-availability Seamless Redundancy (HSR) and Parallel Redundancy Protocol (PRP) reference design. It features Flexibilis Redundant Switch (FRS) intellectual property (IP) implemented on an Altera low-power, low-cost Cyclone-class FPGA or Cyclone V SoC. The reference design simplifies development and implementation of highly reliable mission-critical communications systems in smart grid substation automation equipment.
Lattice Semiconductor introduced a serial sub-LVDS bridge reference design for the Sony IMX136 and IMX104 image sensors. Lattice’s image sensor bridge design helps engineers quickly introduce cameras based on the Sony IMX136 and IMX104. The image sensor bridge design is available now for download, and the MachXO2-1200 (featured in the reference design) is in full production.
Xilinx have created PCI Express x8 Gen3-based designs. The solution features the Virtex-7 field programmable gate array integrated block. All the elements needed for PCI Express x8 Gen3-based designs are now available, including the Virtex-7 X690T FPGA with an integrated PCI express block, ISE Design Suite 14.1 software tool support, a DMA engine provided by third-party Xilinx Alliance Program members, and a 1866 Mb/s DDR3 external memory interface.