'IP Core' Category Archive

Xilinx Virtex-5 SX240T FPGA and Floating Point Operator IP Core v4

Posted by Ken Cheung in FPGA, IP Core on Monday, May 12, 2008

Xilinx, Inc. (Nasdaq: XLNX) introduced the Virtex(R)-5 SX240T FPGA device and version v4.0 of the Floating-Point Operator (FPO) IP core. The SXT240T is the latest member of the 65nm Virtex-5 SXT FPGA platform, which is optimized for high-performance digital signal processing (DSP). With up to 528 GMACs of multiply-and-accumulate performance and over 190 GFLOPS of [...]

Safety Critical DO-254 Nios II Embedded Processor

Posted by Ken Cheung in IP Core on Monday, April 28, 2008

Altera Corporation (NASDAQ:ALTR) and HCELL Engineering has developed a safety-critical version of Altera's Nios® II embedded processor. The embedded processor core complies with the objectives and requirements of the DO-254 hardware avionic standard and meets the highest design-assurance levels. This safety-critical version of the Nios II processor is offered through HCELL Engineering to customers who [...]

DO-254 Global Partner Network

Posted by Ken Cheung in IP Core, Tool on Monday, April 28, 2008

Altera Corporation (NASDAQ:ALTR) launched the DO-254 Global Partner Network. Altera, Aldec, Geensys, HighRely, and HCELL Engineering provide a comprehensive environment of DO-254-certifiable intellectual property (IP) cores, in-hardware verification flows and documentation. The inaugural partners provide specialty solutions and services that enable Altera® FPGA and HardCopy® ASIC solutions to be quickly approved and implemented in avionics [...]

Northwest Logic PCI Express 2.0 for Xilinx Virtex-5FXT

Posted by Ken Cheung in IP Core on Monday, April 21, 2008

Northwest Logic announced the immediate availability of a high-performance, hardware-proven PCI Express® 2.0 solution for Xilinx's Virtex®-5 FXT platform. The solution combines Northwest Logic's full-featured PCI Express 2.0 Core (5Gbit/s), a high-performance, on-demand, multi-engine DMA Back-End Core, DMA Driver (Windows or Linux) and PCI Express GUI to provide a complete, pre-packaged PCI Express 2.0 solution. [...]

LEON3 SPARC Soft Processor

Posted by Ken Cheung in IP Core on Wednesday, April 16, 2008

eASIC Corporation announced the availability of Gaisler Research's LEON3 SPARC Soft Processor. eASIC and Gaisler Research migrated the LEON3 processor to eASIC's Nextreme family of zero mask-charge ASIC devices and achieved 235MHz performance, shattering the performance achievable using high performance FPGAs. Customers now have immediate access to the LEON3 processor and GRLIB IP library for [...]

Synplicity ReadyIP Program

Posted by Ken Cheung in IP Core on Tuesday, April 15, 2008

Synplicity®, Inc. (NASDAQ:SYNP) introduced the ReadyIP Initiative, a program that takes aim at simplifying the access, evaluation, and use of intellectual property (IP) for FPGA-based system design. The ReadyIP program delivers the industry's first and complete universal, encrypted design methodology for FPGA implementation, allowing users to incorporate and easily integrate IP from several third-party vendors [...]

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