Oregano IEEE-1588 IP Cores for LatticeECP3, LatticeECP2M FPGA Devices
Lattice Semiconductor and Oregano Systems introduced IEEE-1588 Timing Node System IP cores for the LatticeECP3 and LatticeECP2M FPGA families. The SoC-class IP cores are syn1588 Clock_S, syn1588 Clock_M, and syn1588 VIP. The syn1588 VIP is a single chip IEEE 1588 solution. The syn1588 Clock_S IP core offers the full syn1588 technology with a minimum amount [...]
MP32 MIPS-based Soft Core Processor for Altera FPGA and ASIC Devices
Altera, MIPS Technologies and System Level Solutions (SLS) teamed together on the MP32 soft core processor. The MP32 is a MIPS-based, FPGA-optimized soft processor for Altera’s FPGA and ASIC devices. The MP32 processor is available now from SLS. The soft processor is royalty free and sold on an unlimited use basis when targeting Altera’s FPGA [...]
Lattice Serial RapidIO 2.1 Endpoint IP Core Supports 4 x 3.125Gbps
Lattice Semiconductor has extended the Serial RapidIO 2.1, Level 1 endpoint core to support 4 x 3.125Gbps. The previous version of the LatticeECP3 FPGA IP core supported 1x and 2x up to 3.125Gbps and 4x up to 2.5Gbps. The Lattice core can be used with the Lattice Advanced Mezzanine Card (AMC) form factor platform. The [...]
PLDA EZDMA IP Solution
The PLDA’s EZDMA IP is a DMA solution. The IP features a vendor-agnostic user interface and seamless device migration. It is configurable for resource optimization and customizable to fit specific customer requirements. The PLDA EZDMA solution supports the Aldec Riviera-PRO for Linux and Active-HDL for Windows verification tools for FPGA development. PLDA’s EZDMA IP solution [...]
Xilinx Broadcast Real-Time Video Engine Targeted Design Platform
Xilinx introduced their Broadcast Real-Time Video Engine Targeted Design Platform. The Real-Time Video Engine Targeted Design Platform consists of a broadcast-quality Video and Image Processing IP pack. The Xilinx Video and Imaging Processing IP pack is priced at $3,000 and will be available at the end of April. Xilinx also rolled out the SMPTE2022 IP [...]
High-Definition Wide Dynamic Range Video Surveillance Chipset
Altera, Apical, and AltaSens teamed together on a chipset for HD WDR video surveillance. The new chipset features an Altera Cyclone IV E FPGA and a security chip that supports Apical’s HD WDR full image signal processing (ISP) pipeline IP and AltaSens’ 1080p60 A3372E3-4T image sensor. Engineers can download the evaluation IP, Apical’s Image Signal [...]
Compression and Encryption IP Cores for LatticeECP3 FPGA
Lattice Semiconductor and Helion Technology teamed on a family of compression and encryption IP cores for the LatticeECP3 FPGA devices. The new portfolio consists of the Payload Compression System core, LZRW lossless compression core, Fast Hash core, and Modular Exponentiation core. The compression and encryption IP cores for the LatticeECP3 FPGA are available now.
PCIEXPAIF Application Interface Core for Altera, Xilinx FPGA PCIe Hard IP
CAST announced their PCIEXPAIF IP Core for integrating PCI Express in an FPGA-based system. The IP core includes a high-level interface between system buses like AMBA AXI4 and the PCI Express hard macro blocks available from Altera and Xilinx. The PCIEXPAIF IP Core integrates a completer controller and DMA controller with up to eight DMA [...]
Altera EFEC7 and EFEC20 100G IP Cores
Altera introduced the EFEC7 and EFEC20 enhanced forward error correction (EFEC) IP cores. The multi-dimensional IP cores are optimized for high performance Stratix IV and Stratix V series FPGA devices. The EFEC7 and EFEC20 were developed by Altera’s Newfoundland Technology Centre (formerly Avalon Microelectronics). They are ideal for 100G applications such as metro and long-haul [...]
ESCRYPT CycurCORE Cryptographic IP Cores for Microsemi FPGA Devices
ESCRYPT has designed several new CycurCORE cryptographic IP cores for Microsemi’s FPGA devices. The cryptographic cores feature enhanced resistance to differential power analysis (DPA). The IP cores support all common cryptographic primitives, such as support for symmetric algorithms with AES, asymmetric cryptographic functions with ECC and RSA, and hash functions with SHA-1, the SHA-2 family, [...]
« Newer Posts || Older Posts »
If you are familiar with RSS feeds, you can also sign up for our free blog feed. Our RSS feed is updated in real-time while our newsletter is updated daily.
