Mylium FPGA-based HD Graphics Controller
Mylium recently completed work on their new HD Graphics Controller IP for embedded systems. The FPGA-based HD graphics controller features typical resource usage of 1315 slice registers (Xilinx Spartan 6). The core has a resolution up to 1920×1080. It has a simple interface and a low number of pins. The Mylium IP core works with [...]
Xilinx SMPTE 2022-5/-6 IP Core for VoIP Broadcasting
Xilinx rolled out their SMPTE 2022-5/-6 intellectual property core. The core is ideal for developing internet protocol based systems needed to reduce the cost of transporting raw, high-bit video from remote events, to studios, to post editing houses, and other points along the production process. The Xilinx SMPTE 2022-5/-6 intellectual property core is available now [...]
RF Engines HyperSpeed Plus Pipeline Fast Fourier Transform IP Cores
RF Engines has enhanced its HyperSpeed PFFT cores from its family of Digital Signal Processing (DSP) solutions to create the new HyperSpeed Plus cores. The Pipeline Fast Fourier Transform (PFFT) IP cores feature data rates in excess of 52 Giga samples per second (2048 point FFT implemented on a Xilinx Virtex-6 FPGA device). The HyperSpeed [...]
CAST 32-bit BA22 Processor Cores for Embedded Systems
CAST announced their royalty-free BA22 Processor IP Family for ASICs and FPGAs. The new IP cores are based on the BA22 design sourced from Beyond Semiconductor. The BA22 processor cores feature pipelined 32-bit RISC BA22 architecture, caches and memory management units, up to 32 general purpose registers, enhanced arithmetic processing capabilities (divider and floating point [...]
Lattice PCI Express 2.0 Solution
According to Lattice Semiconductor, their solution is interoperable with existing PCIe 2.0 supported systems. At a recent PCI-SIG workshop, the LatticeECP3 FPGA and its PCI Express (PCIe) IP core passed PCI-SIG PCIe v2.0 compliance and interoperability testing for 1- and 4-lane configurations. As a result, the LatticeECP3 FPGA family is now compliant with the PCI [...]
Barco Silex BA411E Universal AES Crypto Engine
Barco Silex introduced BA411E, which is an enhanced version of their multi-purpose AES crypto engine. The BA411E IP core supports multi-pipelined architectures, multiple data path configurations, and a wide range of ciphering modes. With the universal AES crypto engine, S-boxes can be efficiently implement as simple logic for ASIC or as memories for FPGA. The [...]
Flexibilis Ethernet Switch IP Cores for LatticeECP3 FPGA Devices
Lattice Semiconductor and Flexibilis introduced Flexibilis Ethernet Switch (FES) IP cores for LatticeECP3 FPGAs. The Ethernet switch IP cores can operate at 10Mbps/100Mbps/1Gbps, support Ethernet Layer 2, switch with Gigabit forwarding capacity per port, support Quality of Service with up to four queues per port, and support Gigabit Fiber optic and Gigabit twisted pair copper [...]
Chip Path Semiconductor IP Centric Design for ASIC, FPGA, ASSP
Chip Path Design Systems introduced their new approach to semiconductor IP chip design. Their methodology focuses on a common Semantic-IC Specification with the ability to map to multiple implementation styles and understanding of complete project costs. Their Semiconductor IP Centric Design results in visibility of timelines and costs across ASIC (Application Specific Integrated Circuit), FPGA [...]
Xilinx Goes Shopping Again, Acquires Sarance Technologies
Xilinx has acquired Sarance Technologies. The acquisition will help Xilinx increase and accelerate the displacement of ASSPs and ASICs in many 40G/100G and beyond programs. Sarance Technologies is a supplier of ASIC and FPGA IP cores for packet processing. The cores include Interlaken IP, classification and traffic management IP.
Xilinx Acquires Modelware, Debuts 100G Traffic Management Reference Design
Xilinx has acquired Modelware, which is a provider of traffic management/packet processing silicon intellectual property (IP) cores and reference designs that simplify system development and enable greater differentiation for networking applications supporting 10G, 40G, 100G and beyond. Xilinx also announced a FPGA-based 100G traffic management reference design for speeding evaluation and implementation of high bandwidth [...]
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