Reflex CES (Custom Embedded Systems) introduced the Aurora-like IP core. It is based on Altera FPGA devices. The Reflex CES IP core enables interoperability between Xilinx Virtex-6 LXT and Altera Stratix IV and Stratix V GX FPGAs. The Reflex CES Aurora-like 8B/10B IP Core is available now with VHDL source code, test-benches, a reference design and user guide. Reflex CES plans to ship an Aurora-like IP Core that supports communication between FPGAs with a 64B/66B protocol at 10 Gbps.
CAST announced the H264-HP-E video encoder IP core. The ISO/IEC 14496-10 and ITU-T H.264 High Profile specification compliant H264-HP-E video encoder IP core is sourced from Alma Technologies. It is available now and is ideal for HD broadcast, professional video cameras, and video storage. An intra-only version features extremely low latency for real-time applications, and is suitable for AVC-Intra 50 and 100 implementations.
RFEL announced a new family of video processing IP cores. The IP FPGA cores can be supplied with standard software interface frameworks to simplify their deployment. If required, RFEL can modify the cores to meet the requirements of constrained resources or legacy platforms. The new video processing FPGA IP cores are available now, either as standalone cores or as part of a system solution created by RFEL to meet a customer’s requirements.
PLDA introduced their QuickUDP, which is a 10Gb UDP Hardware stack IP core for FPGA devices. The QuickUDP IP solution is a 100% RTL-designed IP, compliant with the IEEE802.3 specification and supports the ARP, IPv4, ICMP, IGMP, and UDP protocols. The PLDA QuickUDP 10G UDP Hardware Stack IP is available now from PLDA. The PLDA QuickUDP can be integrated into Altera-based and Xilinx-based FPGA designs.
Altera introduced a single-chip, multi-rate OTN (optical transport network) muxponder solution for 100G network aggregation. The multi-rate muxponder IP solution is based on Altera’s 28nm Stratix V FPGA devices. The solution enables engineers to customize systems and target FPGA architectures that are optimized for specific design requirements. The multirate 100G muxponder IP solution expands the capabilities of current networks by enabling developers to integrate emerging client types into their networks, such as 16G Fibre Channel.
Vanguard Software Solutions introduced their AVC-I encoder and decoder core for FPGA devices. A SVC codec core will be available in the fourth quarter. In addition, VSS is also developing a new HEVC FPGA core that will be available next year. The HEVC core will provide customers with access to real-time, HEVC functionality with FPGA flexibility.
PLDA recently introduced their QuickTCP IP, which is a 10Gb TCP/IP Hardware stack IP core. It features an AMBA AXI4 user interface that enables instant integration into either Altera-based or Xilinx-based FPGA designs. PLDA QuickTCP is a 100% RTL designed IP. It is compliant with the IEEE802.3 specification and supporting the ARP, IPv4, ICMP, and TCP protocols. The PLDA QuickTCP IP solution is available now from PLDA.
The Xilinx Virtex-6Q Field Programmable Gate Array (FPGA) family is a high performance defense-grade, programmable solution for major defense applications. The combination of Virtex-6Q FPGA with the Xilinx Security Monitor (SECMON) IP core provides a secure platform for Aerospace and Defense (A&D) designs used in critical AT applications. The SECMON IP core offers a level of Anti-Tamper (AT) protection that will further strengthen the secure capabilities of the Virtex-6Q family of FPGAs.
Altera and TSMC teamed on a heterogeneous 3D IC test vehicle. The process uses TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) integration process. Altera is the first semiconductor company to develop and complete characterization of a heterogeneous test vehicle using TSMC’s CoWoS process. This and additional test vehicles enable Altera to quickly test the capabilities and reliability of 3D ICs to ensure they meet yield and performance targets.
Xilinx introduced their dual 100G Gearbox solution, which features a 28nm Virtex-7 HT FPGA and dual 100G Gearbox intellectual property cores. The new Xilinx solution enables equipment vendors to connect 100 Gbps interfaces with up to two CFP2 optical modules while lowering the overall BOM by reducing chip count and allowing integration with OTN framers as well as 100G bridges into a single chip. The programmability of the Virtex-7 HT FPGA ensures that the equipment vendors can easily keep up with changes in standards that are still evolving in the optical, Ethernet and OTN market space.