FPGA Blog » IP Core

CAST UDPIP IP Core

Ken Cheung — Tue, 20 Dec 2011 16:42:09 +0000

CAST introduced the UDPIP IP core. The CAST UDPIP is a hardware implementation of the User Datagram Protocol (UDP), which is a fast, simple, transport layer protocol that works without the handshaking and error correction of the more rigorous Transmission Control Protocol (TCP). The UDPIP IP core is available now in Verilog or as an optimized netlist for Altera and Xilinx FPGAs. Integration with MAC cores from CAST, FPGA vendors, or other sources is available. Integration with CAST compression cores (e.g., the H.264 encoder) is also available.

World’s Fastest 8051 CPU: Quad-Pipelined Microcontroller IP Core

Ken Cheung — Thu, 01 Dec 2011 17:13:15 +0000

Digital Core Design announced the DQ80251 Core. It is a quad-pipelined, speed optimized soft core of a 16-bit/32-bit embedded microcontroller. The DCD DQ80251 IP core is the world’s fastest 8051 microprocessor solution. With a confirmed Dhrystone 2.1 benchmark, the DQ80251 IP core is up to 56.8 times faster than the original 8051 and 4.81 times faster than the original 80C251 at the same clock frequency. The DQ80251 includes a fully automated testbench and a complete set of tests.

Serial RapidIO Gen 2 v1.2 Endpoint, CPRI v4.1, and JESD204B v.1.1 IP Cores

Ken Cheung — Tue, 22 Nov 2011 16:46:49 +0000

Xilinx recently introduced the Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE, CPRI v4.1 LogiCORE, and JESD204B v.1.1 LogiCORE IP cores. The Xilinx three LogiCORE IP cores support connectivity standards and will help developers address design challenges in building new wireless equipment with higher system capacities. The Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE IP, JESD204 v1.1 LogiCORE IP , and CPRI v4.1 LogiCORE IP are ideal for building programmable, flexible and cost effective 3G+/4G wireless base stations. They are available in Xilinx’s ISE Design Suite 13.3 and can be evaluated free of charge.

CAST NAND Flash Controller IP Core v6 Supports Latest High-Speed Memory Devices

Ken Cheung — Thu, 17 Nov 2011 16:24:18 +0000

CAST, Inc. rolled out version six of their NAND Flash Memory Controller IP core. The CAST NANDFLASH-CTRL Core is available in synthesizable RTL for ASICs or optimized netlists for FPGAs. Versions of the royalty-free controller core range from a lean, asynchronous-only core (for long-term or boot-code storage applications) through a full-featured, high-speed core (for applications needing the full bandwidth of the latest memory devices).

Altera RapidIO MegaCore Function IP Core

Ken Cheung — Mon, 26 Sep 2011 18:05:22 +0000

Altera introduced their RapidIO MegaCore Function IP core. It is implemented in a Stratix IV GX FPGA with a Serial RapidIO Gen 2 switch from Integrated Device Technology (IDT). The IP core is the first Serial RapidIO Gen2 FPGA-based solution. The RapidIO MegaCore Function IP core is available now for download. It is available as encrypted IP or as source code for complete user control.

Mylium FPGA-based HD Graphics Controller

Ken Cheung — Fri, 23 Sep 2011 04:19:01 +0000

Mylium recently completed work on their new HD Graphics Controller IP for embedded systems. The FPGA-based HD graphics controller features typical resource usage of 1315 slice registers (Xilinx Spartan 6). The core has a resolution up to 1920×1080. It has a simple interface and a low number of pins. The Mylium IP core works with both external 8/16/32-bit microcontrollers and soft-processors.

Xilinx SMPTE 2022-5/-6 IP Core for VoIP Broadcasting

Ken Cheung — Fri, 09 Sep 2011 14:06:08 +0000

Xilinx rolled out their SMPTE 2022-5/-6 intellectual property core. The core is ideal for developing internet protocol based systems needed to reduce the cost of transporting raw, high-bit video from remote events, to studios, to post editing houses, and other points along the production process. The Xilinx SMPTE 2022-5/-6 intellectual property core is available now through early access. The core will be available as a Xilinx LogiCORE IP core in the first quarter of 2012.

RF Engines HyperSpeed Plus Pipeline Fast Fourier Transform IP Cores

Ken Cheung — Thu, 08 Sep 2011 16:14:01 +0000

RF Engines has enhanced its HyperSpeed PFFT cores from its family of Digital Signal Processing (DSP) solutions to create the new HyperSpeed Plus cores. The Pipeline Fast Fourier Transform (PFFT) IP cores feature data rates in excess of 52 Giga samples per second (2048 point FFT implemented on a Xilinx Virtex-6 FPGA device). The HyperSpeed Plus cores are available now for licence in netlist form from RFEL.

CAST 32-bit BA22 Processor Cores for Embedded Systems

Ken Cheung — Fri, 29 Jul 2011 14:35:49 +0000

CAST announced their royalty-free BA22 Processor IP Family for ASICs and FPGAs. The new IP cores are based on the BA22 design sourced from Beyond Semiconductor. The BA22 processor cores feature pipelined 32-bit RISC BA22 architecture, caches and memory management units, up to 32 general purpose registers, enhanced arithmetic processing capabilities (divider and floating point units), power-management unit, interactive JTAG-based debug capability, 1.41 DMIPS/MHz, frequencies from 50 MHz to over 300 MHz, 12,000 to 38,000 gates, and require only 0.023 mW/MHz (in a 65nm process).

Lattice PCI Express 2.0 Solution

Ken Cheung — Tue, 05 Jul 2011 17:03:56 +0000

According to Lattice Semiconductor, their solution is interoperable with existing PCIe 2.0 supported systems. At a recent PCI-SIG workshop, the LatticeECP3 FPGA and its PCI Express (PCIe) IP core passed PCI-SIG PCIe v2.0 compliance and interoperability testing for 1- and 4-lane configurations. As a result, the LatticeECP3 FPGA family is now compliant with the PCI Express 2.0 specification at 2.5Gbps. Lattice also worked with Trellisys on a PCIe Bus Functional Model (BFM) for Lattice’s PCI Express x1 and x4 IP Cores.