FPGA Blog » IP Core

PLDA Unveils QuickTCP 10G TCP/IP Stack IP Core for Altera, Xilinx FPGA

Ken Cheung — Wed, 09 May 2012 16:12:20 +0000

PLDA recently introduced their QuickTCP IP, which is a 10Gb TCP/IP Hardware stack IP core. It features an AMBA AXI4 user interface that enables instant integration into either Altera-based or Xilinx-based FPGA designs. PLDA QuickTCP is a 100% RTL designed IP. It is compliant with the IEEE802.3 specification and supporting the ARP, IPv4, ICMP, and TCP protocols. The PLDA QuickTCP IP solution is available now from PLDA.

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Xilinx Defense-Grade Virtex-6Q FPGA Includes Anti-Tamper Protection

Ken Cheung — Tue, 27 Mar 2012 16:58:22 +0000

The Xilinx Virtex-6Q Field Programmable Gate Array (FPGA) family is a high performance defense-grade, programmable solution for major defense applications. The combination of Virtex-6Q FPGA with the Xilinx Security Monitor (SECMON) IP core provides a secure platform for Aerospace and Defense (A&D) designs used in critical AT applications. The SECMON IP core offers a level of Anti-Tamper (AT) protection that will further strengthen the secure capabilities of the Virtex-6Q family of FPGAs.

Altera, TSMC Use CoWoS Process to Create Heterogeneous 3D IC Test Vehicle

Ken Cheung — Thu, 22 Mar 2012 18:33:51 +0000

Altera and TSMC teamed on a heterogeneous 3D IC test vehicle. The process uses TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) integration process. Altera is the first semiconductor company to develop and complete characterization of a heterogeneous test vehicle using TSMC’s CoWoS process. This and additional test vehicles enable Altera to quickly test the capabilities and reliability of 3D ICs to ensure they meet yield and performance targets.

Xilinx Introduces Dual 100 Gbps Gearbox Solution

Ken Cheung — Mon, 05 Mar 2012 18:18:26 +0000

Xilinx introduced their dual 100G Gearbox solution, which features a 28nm Virtex-7 HT FPGA and dual 100G Gearbox intellectual property cores. The new Xilinx solution enables equipment vendors to connect 100 Gbps interfaces with up to two CFP2 optical modules while lowering the overall BOM by reducing chip count and allowing integration with OTN framers as well as 100G bridges into a single chip. The programmability of the Virtex-7 HT FPGA ensures that the equipment vendors can easily keep up with changes in standards that are still evolving in the optical, Ethernet and OTN market space.

Lattice Semiconductor Adds MIPI Battery Interface to iCE40 mobileFPGA

Ken Cheung — Fri, 02 Mar 2012 16:43:21 +0000

Lattice Semiconductor is supporting the MIPI Battery Interface (BIF) standard within the iCE40 mobileFPGA family of products. The MIPI BIF single-wire specification is an industry-created and adopted standard. It accelerates the design and use of smart batteries in mobile devices. Lattice Semiconductor is a participating member of the MIPI BIF committee.

CAST UDPIP IP Core

Ken Cheung — Tue, 20 Dec 2011 16:42:09 +0000

CAST introduced the UDPIP IP core. The CAST UDPIP is a hardware implementation of the User Datagram Protocol (UDP), which is a fast, simple, transport layer protocol that works without the handshaking and error correction of the more rigorous Transmission Control Protocol (TCP). The UDPIP IP core is available now in Verilog or as an optimized netlist for Altera and Xilinx FPGAs. Integration with MAC cores from CAST, FPGA vendors, or other sources is available. Integration with CAST compression cores (e.g., the H.264 encoder) is also available.

World’s Fastest 8051 CPU: Quad-Pipelined Microcontroller IP Core

Ken Cheung — Thu, 01 Dec 2011 17:13:15 +0000

Digital Core Design announced the DQ80251 Core. It is a quad-pipelined, speed optimized soft core of a 16-bit/32-bit embedded microcontroller. The DCD DQ80251 IP core is the world’s fastest 8051 microprocessor solution. With a confirmed Dhrystone 2.1 benchmark, the DQ80251 IP core is up to 56.8 times faster than the original 8051 and 4.81 times faster than the original 80C251 at the same clock frequency. The DQ80251 includes a fully automated testbench and a complete set of tests.

Serial RapidIO Gen 2 v1.2 Endpoint, CPRI v4.1, and JESD204B v.1.1 IP Cores

Ken Cheung — Tue, 22 Nov 2011 16:46:49 +0000

Xilinx recently introduced the Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE, CPRI v4.1 LogiCORE, and JESD204B v.1.1 LogiCORE IP cores. The Xilinx three LogiCORE IP cores support connectivity standards and will help developers address design challenges in building new wireless equipment with higher system capacities. The Serial RapidIO Gen 2 v1.2 Endpoint LogiCORE IP, JESD204 v1.1 LogiCORE IP , and CPRI v4.1 LogiCORE IP are ideal for building programmable, flexible and cost effective 3G+/4G wireless base stations. They are available in Xilinx’s ISE Design Suite 13.3 and can be evaluated free of charge.

CAST NAND Flash Controller IP Core v6 Supports Latest High-Speed Memory Devices

Ken Cheung — Thu, 17 Nov 2011 16:24:18 +0000

CAST, Inc. rolled out version six of their NAND Flash Memory Controller IP core. The CAST NANDFLASH-CTRL Core is available in synthesizable RTL for ASICs or optimized netlists for FPGAs. Versions of the royalty-free controller core range from a lean, asynchronous-only core (for long-term or boot-code storage applications) through a full-featured, high-speed core (for applications needing the full bandwidth of the latest memory devices).

Altera RapidIO MegaCore Function IP Core

Ken Cheung — Mon, 26 Sep 2011 18:05:22 +0000

Altera introduced their RapidIO MegaCore Function IP core. It is implemented in a Stratix IV GX FPGA with a Serial RapidIO Gen 2 switch from Integrated Device Technology (IDT). The IP core is the first Serial RapidIO Gen2 FPGA-based solution. The RapidIO MegaCore Function IP core is available now for download. It is available as encrypted IP or as source code for complete user control.