EnSilica eSi-RISC Validates with Precision Synthesis FPGA Design Flow
EnSilica’s range of eSi-RISC embedded processor cores and eSi-Comms library of communications IP has been fully validated for use in Mentor Graphics’ Precision Synthesis FPGA design flow, enabling design engineers to easily implement them on any FPGA device. eSi-RISC’s single architecture is scalable over a range of embedded applications. A high level of configurability enables [...]
Actel CoreFFT v4.0 Fast Fourier Transform IP Core
Actel introduced CoreFFT v4.0 intellectual property (IP) core for Fast Fourier Transform (FFT). CoreFFT v4.0 makes use of radiation-protected, multiply-accumulate blocks embedded on-chip in Actel’s radiation-tolerant RTAX-DSP FPGA devices to deliver a flexible, fully configurable radix-2 decimation-in-time (DIT) burst I/O FFT for high reliability, radiation-tolerant applications. CoreFFT v4.0 is now available for ordering. The Actel [...]
Actel CoreFIR v4.0 IP Core Generator for RTAX-DSP FPGA Devices
CoreFIR v4.0, from Actel, is a core generator for finite impulse response (FIR) filters. The core generator uses a distributed arithmetic implementation methodology to create FPGA-based digital filters. CoreFIR v4.0 is optimized for use with Actel RTAX-DSP devices and leverages the FPGA’s embedded radiation-tolerant multiply-accumulate blocks. The IP core is ideal for radar, sonar, ultrasound, [...]
Helion IONOS Video Pipeline IP for Lattice FPGA Devices
Lattice Semiconductor and Helion GmbH teamed on Intellectual Property (IP) cores for the video security and surveillance camera market. Helion’s IONOS video pipeline IP and Vesta evaluation platform targets the LatticeXP2, LatticeECP2M, and LatticeECP3 FPGA families. The Helion Vesta evaluation platform is a completely self-contained platform that enables the development and realization of image pipelines [...]
Tokyo Electron Device MECHATROLINK-III IP Core for Xilinx Spartan-6 FPGA
Tokyo Electron Device has developed an IP core compatible with the MECHATROLINK-III standard for implementation with the low-cost Xilinx Spartan-6 FPGA family. The MECHATROLINK-III specification is an open motion field network communications standard established by the Iruma, Saitama Prefecture, Japan-based MECHATROLINK Members Association. Tokyo Electron Device’s MECHATROLINK-III compliant IP core for Spartan-6 FPGAs will be [...]
PLDA XpressRich3 PCI Express 3.0 Based IP Core for FPGA, ASIC Devices
PLDA introduced the XpressRich3 IP core for FPGAs and ASICs based on the forthcoming PCIe 3.0 specification, currently under development within the PCI-SIG. The PLDA XpressRich3 core features an architecture that seamlessly allows both ASIC and FPGA implementations. The PLDA XpressRich3 IP will be available for review at the PCI-SIG Developers Conference, which will be [...]
Actel Libero Features Access to Over 50 IP Cores
Actel’s Libero Gold and Platinum editions now include access to over fifty IP cores. The Libero Gold Edition, which supports Actel FPGAs up to 1.5 million system gates, includes obfuscated versions of the Actel IP cores that can be easily used in designs but cannot be modified. The Libero Platinum edition supports Actel FPGA devices [...]
Tokyo Electron Device V-by-One HS IP Core for Xilinx FPGA Spartan-6
Tokyo Electron Device (TED) introduced the V-by-One HS IP Core for Xilinx FPGA Spartan-6. V-by-One HS is an open standard for allowing transmission of large amounts of video and control data to support the higher frame rates and the higher resolutions required by next-generation flat-panel displays. It enables high-speed serial data transfer technology capable of [...]
Actel Core1553 Development Kit
Actel introduced the Core1553 Development Kit, which is essentially a self-contained benchtop 1553 bus development system. The kit enables the development and testing of MIL-STD-1553B development using Actel’s Core1553BRM IP core. The Core1553 Development Kit (part number CORE1553-DEV-KIT) is available now for US $3620. The Core1553BRM core is licensed separately and is not included in [...]
Actel IP Cores for SmartFusion Intelligent Mixed Signal FPGAs
Actel introduced intellectual property (IP) cores for SmartFusion intelligent mixed signal FPGAs. A large library of Actel IP cores are included in the Libero Integrated Design Environment (IDE) IP bundle, with obfuscated-RTL version included with the free Libero Gold license, and RTL-source version included with the $2,500 Libero Platinum license. The library of Actel’s IP [...]
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