FPGA Blog - field programmable gate array and structured asic

'IP Core' Category Archive

Automotive Pixel Link IP for Xilinx Automotive Spartan-6 FPGA Family

Posted by Ken Cheung in IP Core on Wednesday, March 3, 2010

Xilinx and Inova Semiconductors announced an Automotive Pixel Link (APIX) IP solution for the Xilinx Automotive (XA) family of low-cost Spartan-6 field programmable gate arrays (FPGAs). The configurable core supports multiple high-bandwidth video and communications links in a single device to transfer high-quality, real-time video from two or more cameras or processing units to in-vehicle [...]

Silicon Image CineramIC 4K and 3D H.264 Digital Video Decoder IP Core

Posted by Ken Cheung in IP Core on Wednesday, December 16, 2009

Silicon Image introduced the cineramIC 4K and 3D H.264 digital video decoder IP core. With its high performance, low cost and high-quality video imaging, the cineramIC IP core can be integrated into System-on-Chips (SoCs) for next-generation digital TV (DTV), set-top-box (STB) and camcorder applications, as well as professional video editing, broadcast, medical, and surveillance FPGA [...]

DapTechnology Gigabit IEEE 1394b FireWire SOC Solution

Posted by Ken Cheung in IP Core on Tuesday, November 24, 2009

DapTechnology demonstrated the world’s first high speed S3200 3.2 Gigabit IEEE 1394b FireWire system-on-a-chip (SOC) solution at VISION 2009 in Stuttgart, Germany. The demonstration showed video data being transported from a Xilinx development board through a 10 meter standard FireWire cable to a PCI Express board within a host computer. The company is spearheading this [...]

Evatronix NAND Flash Memory Controller Supports ONFi 2.2 Specifications

Posted by Ken Cheung in IP Core on Monday, November 23, 2009

Evatronix has updated NAND Flash memory controller to meet the 2.2 specifications of the Open NAND Flash interface (ONFi) and now fully supports the newest High Speed NAND Flash. This enables the development of applications that will leverage the ability of new memory technologies to operate with speeds of up to 200 MB per second. [...]

Serial RapidIO 2.1 Endpoint Soft IP Core for LatticeECP3 FPGA

Posted by Ken Cheung in IP Core on Monday, November 23, 2009

Lattice Semiconductor has licensed the Serial RapidIO 2.1 endpoint soft IP core for the LatticeECP3 FPGA family from Praesum. Lattice has full rights to use and sub-license the Serial RapidIO IP core. The core supports 1x, 2x, and 4x lane configurations at up to 3.125Gbps lane speeds, offering the lowest cost, lowest power programmable SRIO [...]

New Actel DSP IP Cores for RTAX-DSP FPGAs

Posted by Ken Cheung in IP Core on Wednesday, November 18, 2009

Actel introduced three highly configurable DSP IP cores for the RTAX2000D and RTAX4000D DSP FPGAs. The new cores enable designers to easily create common DSP functions such as filters (FIR, IIR) and transforms (FFT, IFT, DCT). Using a graphical user interface (GUI) embedded in Actel’s Libero Integrated Design Environment (IDE), the cores are targeted to [...]

eSi-1600, eSi-3200, and eSi-3250 Configurable Soft Processor Cores

Posted by Ken Cheung in IP Core on Tuesday, November 17, 2009

EnSilica announced the eSi-1600, eSi-3200, and eSi-3250 highly configurable and low-power soft processor cores. The new processor cores are available immediately for deployment as part of EnSilica’s full specification-to-silicon design service through a number of leading foundries and an FPGA integration service utilizing devices from all the leading vendors.

Altera Serial RapidIO Intellectual Property Core for RapidIO 2.1

Posted by Ken Cheung in IP Core on Tuesday, November 17, 2009

Altera introduced their Serial RapidIO intellectual property (IP) core for the RapidIO 2.1 specification. Altera’s Serial RapidIO IP core supports up to four lanes at 5.0 GBaud per lane, addressing the increased bandwidth and reliability needs of the wireless and military markets. The IP core is optimized for Stratix IV FPGAs with embedded transceivers and [...]

DirectCore Building Blocks Enhancements for xTCA Platform Management

Posted by Ken Cheung in IP Core on Monday, November 16, 2009

Actel teamed with Pigeon Point Systems to develop IP core enhancements for hardware platform management applications. The DirectCore enhancements strengthen the suitability of Actel Fusion mixed-signal FPGAs for local xTCA management controllers, and especially xTCA applications, for which Pigeon Point offers the Board Management Reference (BMR) series.

Jointwave H.264 Encoder IP Cores

Posted by Ken Cheung in IP Core on Friday, October 23, 2009

Jointwave introduced their H.264 series encoder IP core. The Jointwave IP cores support Level 1.0 to 5.1 of H.264 (MPEG-4 Part 10, also called AVC). The cores cover baseline profile, main profile, and high 4:2:2/4:4:4 profile. Compare to competitors’ solutions, Jointwave’s IP core uses less hardware resources. The H.264 encoder features ultra-low frequency, super low [...]

Older Posts »

 
FPGA Blog Newsletter
Don't have time to visit FPGA Blog everyday? Then sign up for our free newsletter. We'll send you an email when we have something to share with you. Your email address will be kept confidential and we will not share, sell, or rent it to anyone. You can unsubscribe at any time by clicking a link in the email.

Enter your email address to sign up for our free newsletter:  

If you are familiar with RSS feeds, you can also sign up for our free blog feed. Our RSS feed is updated in real-time while our newsletter is updated daily.