<?xml version="1.0" encoding="UTF-8"?>
<rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:wfw="http://wellformedweb.org/CommentAPI/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	xmlns:sy="http://purl.org/rss/1.0/modules/syndication/"
	xmlns:slash="http://purl.org/rss/1.0/modules/slash/"
	>

<channel>
	<title>FPGA Blog &#187; Other</title>
	<atom:link href="http://fpgablog.com/posts/category/general/feed/" rel="self" type="application/rss+xml" />
	<link>http://fpgablog.com</link>
	<description>FPGA (field programmable gate array) and structured ASIC information</description>
	<lastBuildDate>Tue, 15 May 2012 17:19:14 +0000</lastBuildDate>
	<language>en</language>
	<sy:updatePeriod>hourly</sy:updatePeriod>
	<sy:updateFrequency>1</sy:updateFrequency>
	<generator>http://wordpress.org/?v=3.3</generator>
		<item>
		<title>Lattice iCE40 mobileFPGA Devices Support MIPI Battery Interface Standard</title>
		<link>http://fpgablog.com/posts/mobile-devices-batteries/</link>
		<comments>http://fpgablog.com/posts/mobile-devices-batteries/#comments</comments>
		<pubDate>Wed, 14 Mar 2012 16:34:59 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Other]]></category>
		<category><![CDATA[batteries]]></category>
		<category><![CDATA[Battery Interface Standard]]></category>
		<category><![CDATA[BIF]]></category>
		<category><![CDATA[BIF Master]]></category>
		<category><![CDATA[iCE40 mobileFPGA]]></category>
		<category><![CDATA[iCEcube2]]></category>
		<category><![CDATA[Lattice Semiconductor]]></category>
		<category><![CDATA[MIPI]]></category>
		<category><![CDATA[mobile devices]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3732</guid>
		<description><![CDATA[Lattice Semiconductor has adopted the MIPI Battery Interface (BIF) standard within the iCE40 mobileFPGA family of products. As an industry-created and adopted standard, the MIPI BIF single-wire specification accelerates the design and use of smart batteries in mobile devices. Lattice Semiconductor is engaged with key customers on the MIPI BIF standard. They plan to make [...]]]></description>
			<content:encoded><![CDATA[<p>Lattice Semiconductor has adopted the MIPI Battery Interface (BIF) standard within the iCE40 mobileFPGA family of products. As an industry-created and adopted standard, the MIPI BIF single-wire specification accelerates the design and use of smart batteries in mobile devices. Lattice Semiconductor is engaged with key customers on the MIPI BIF standard. They plan to make support broadly available through its IP suite during the first half of this year. The MIPI BIF solutions will be free of charge to customers with high-volume mobile applications.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/mobile-devices-batteries/">Lattice iCE40 mobileFPGA Devices Support MIPI Battery Interface Standard</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/mobile-devices-batteries/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/mobile-devices-batteries/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>Altera Packs Two 100G Transponders on a Single FPGA</title>
		<link>http://fpgablog.com/posts/stratix-v-otn-ip/</link>
		<comments>http://fpgablog.com/posts/stratix-v-otn-ip/#comments</comments>
		<pubDate>Thu, 01 Mar 2012 17:57:14 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Other]]></category>
		<category><![CDATA[100G]]></category>
		<category><![CDATA[altera]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Optical Networks]]></category>
		<category><![CDATA[OTN IP]]></category>
		<category><![CDATA[Stratix V]]></category>
		<category><![CDATA[Transponders]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3697</guid>
		<description><![CDATA[Altera created a single-chip, dual 100G transponder solution that is implemented in a 28nm high-performance Stratix V FPGA. With the new dual 100G transponder solution, Altera is now able to deliver density that is unachievable with current solutions and puts them on the path to support data rates of 400G and beyond. Altera is currently [...]]]></description>
			<content:encoded><![CDATA[<p>Altera created a single-chip, dual 100G transponder solution that is implemented in a 28nm high-performance Stratix V FPGA. With the new dual 100G transponder solution, Altera is now able to deliver density that is unachievable with current solutions and puts them on the path to support data rates of 400G and beyond. Altera is currently shipping 28-nm Stratix V FPGAs and OTN IP.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/stratix-v-otn-ip/">Altera Packs Two 100G Transponders on a Single FPGA</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/stratix-v-otn-ip/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/stratix-v-otn-ip/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>LDRA Tool Suite Supports Direct Integration with Altera Nios II Embedded Design Suite</title>
		<link>http://fpgablog.com/posts/soft-core-eds/</link>
		<comments>http://fpgablog.com/posts/soft-core-eds/#comments</comments>
		<pubDate>Fri, 03 Feb 2012 15:44:36 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Other]]></category>
		<category><![CDATA[LDRA Tool Suite Supports Direct Integration with Altera Nios II Embedded Design Suite]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3631</guid>
		<description><![CDATA[Earlier in the week, LDRA announced that they have enhanced the LDRA tool suite to support direct integration with Altera&#8217;s Embedded Design Suite (EDS) for Nios II soft core processors. The LDRA tool suite features templates tailored to specific industry and programming standards. These are delivered pre-populated with standard requirements, simplifying compliance for developers. Combined [...]]]></description>
			<content:encoded><![CDATA[<p>Earlier in the week, LDRA announced that they have enhanced the LDRA tool suite to support direct integration with Altera&#8217;s Embedded Design Suite (EDS) for Nios II soft core processors. The LDRA tool suite features templates tailored to specific industry and programming standards. These are delivered pre-populated with standard requirements, simplifying compliance for developers. Combined with the cost-reduced Nios II platform, LDRA tool suite helps reduce the cost of embedded systems in industries such as automotive, medical, and avionics.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/soft-core-eds/">LDRA Tool Suite Supports Direct Integration with Altera Nios II Embedded Design Suite</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/soft-core-eds/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/soft-core-eds/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>Aldec ALINT 2012.01 Includes Documentation Support for Safety-Critical Designs</title>
		<link>http://fpgablog.com/posts/vhdl-verilog-do-254/</link>
		<comments>http://fpgablog.com/posts/vhdl-verilog-do-254/#comments</comments>
		<pubDate>Thu, 26 Jan 2012 17:00:05 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Other]]></category>
		<category><![CDATA[Aldec]]></category>
		<category><![CDATA[ALINT 2012.01]]></category>
		<category><![CDATA[Automotive]]></category>
		<category><![CDATA[avionics]]></category>
		<category><![CDATA[Designs]]></category>
		<category><![CDATA[DO-254]]></category>
		<category><![CDATA[Documentation]]></category>
		<category><![CDATA[IEC 61508]]></category>
		<category><![CDATA[IEC 61513]]></category>
		<category><![CDATA[ISO 26262]]></category>
		<category><![CDATA[nuclear]]></category>
		<category><![CDATA[safety-critical]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3591</guid>
		<description><![CDATA[Aldec rolled out ALINT 2012.01. The latest version features documentation support that addresses the strict guidelines placed on various safety-critical industries such as DO-254 for avionics, IEC 61508/61513 for nuclear and ISO 26262 for automotive. The ability to generate a report with complete analysis of detected violations and justification of waivers can help engineers decrease [...]]]></description>
			<content:encoded><![CDATA[<p>Aldec rolled out ALINT 2012.01. The latest version features documentation support that addresses the strict guidelines placed on various safety-critical industries such as DO-254 for avionics, IEC 61508/61513 for nuclear and ISO 26262 for automotive. The ability to generate a report with complete analysis of detected violations and justification of waivers can help engineers decrease the effort in documentation and reporting. ALINT 2012.01 with support for VHDL or Verilog DO-254 design rule plug-in is available now.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/vhdl-verilog-do-254/">Aldec ALINT 2012.01 Includes Documentation Support for Safety-Critical Designs</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/vhdl-verilog-do-254/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/vhdl-verilog-do-254/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>Cornell University Students Create Interesting FPGA Projects</title>
		<link>http://fpgablog.com/posts/cornell-ece5760-2011/</link>
		<comments>http://fpgablog.com/posts/cornell-ece5760-2011/#comments</comments>
		<pubDate>Thu, 22 Dec 2011 19:22:07 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Other]]></category>
		<category><![CDATA[altera]]></category>
		<category><![CDATA[board]]></category>
		<category><![CDATA[Cornell University]]></category>
		<category><![CDATA[Cyclone II]]></category>
		<category><![CDATA[DE2]]></category>
		<category><![CDATA[Development]]></category>
		<category><![CDATA[ECE 5760]]></category>
		<category><![CDATA[Education]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[students]]></category>
		<category><![CDATA[Terasic]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3567</guid>
		<description><![CDATA[Every year, the brilliant students at Cornell University work on some fabulous projects for their ECE 5760. The students were given the responsibility of choosing their project, then designing and building it. Projects were built using the Altera/Terasic DE2 Development and Education board. This year&#8217;s projects include: prime number generator and RSA encrypter/decrypter, Conway&#8217;s life [...]]]></description>
			<content:encoded><![CDATA[<p>Every year, the brilliant students at Cornell University work on some fabulous projects for their ECE 5760. The students were given the responsibility of choosing their project, then designing and building it. Projects were built using the Altera/Terasic DE2 Development and Education board. This year&#8217;s projects include: prime number generator and RSA encrypter/decrypter, Conway&#8217;s life synthesizer, hand video-tracking virtual piano and drums, finger video-tracking virtual string instrument, and hand video-tracking video game.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/cornell-ece5760-2011/">Cornell University Students Create Interesting FPGA Projects</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/cornell-ece5760-2011/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/cornell-ece5760-2011/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>Xilinx ISE Design Suite v13.2 Supports 28nm 7 FPGA Devices</title>
		<link>http://fpgablog.com/posts/ise-design-suite-13-2/</link>
		<comments>http://fpgablog.com/posts/ise-design-suite-13-2/#comments</comments>
		<pubDate>Thu, 07 Jul 2011 14:10:59 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Other]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[ISE Design Suite]]></category>
		<category><![CDATA[Kintex-7]]></category>
		<category><![CDATA[Virtex-7]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3217</guid>
		<description><![CDATA[Xilinx rolled out version 13.2 of their ISE Design Suite. The latest version features 28nm 7 series support, 25% performance improvement for designs targeting Virtex-7 2000T FPGA devices, PlanAhead design and analysis tool enhancements, partial reconfiguration support for Virtex-7 and Kintex-7 FPGAs, and front-to-back, integrated project management environment. ISE Design Suite 13 is available now. [...]]]></description>
			<content:encoded><![CDATA[<p>Xilinx rolled out version 13.2 of their ISE Design Suite. The latest version features 28nm 7 series support, 25% performance improvement for designs targeting Virtex-7 2000T FPGA devices, PlanAhead design and analysis tool enhancements, partial reconfiguration support for Virtex-7 and Kintex-7 FPGAs, and front-to-back, integrated project management environment. ISE Design Suite 13 is available now. Prices start at $2,995 for the Logic Edition.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/ise-design-suite-13-2/">Xilinx ISE Design Suite v13.2 Supports 28nm 7 FPGA Devices</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/ise-design-suite-13-2/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/ise-design-suite-13-2/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>Silicon Laboratories Si51x XO and VCXO Crystal Oscillators</title>
		<link>http://fpgablog.com/posts/voltage-controlled/</link>
		<comments>http://fpgablog.com/posts/voltage-controlled/#comments</comments>
		<pubDate>Tue, 15 Mar 2011 14:13:22 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Other]]></category>
		<category><![CDATA[Crystal Oscillator]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Oscillators]]></category>
		<category><![CDATA[Si51x]]></category>
		<category><![CDATA[Silicon Labs]]></category>
		<category><![CDATA[VCXO]]></category>
		<category><![CDATA[XO]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=2947</guid>
		<description><![CDATA[Silicon Laboratories introduced the Si51x XO/VCXO family of crystal oscillators (XOs) and voltage-controlled XOs (VCXOs). The Si512/3 dual-frequency XO devices can replace two discrete XOs and a multiplexer in networking, broadcast video and other applications that use multi-rate SerDes devices and FPGA devices. Si510/511 single-frequency XO is priced from $2.10 to $3.69 (in 10,000-unit quantities). [...]]]></description>
			<content:encoded><![CDATA[<p>Silicon Laboratories introduced the Si51x XO/VCXO family of crystal oscillators (XOs) and voltage-controlled XOs (VCXOs). The Si512/3 dual-frequency XO devices can replace two discrete XOs and a multiplexer in networking, broadcast video and other applications that use multi-rate SerDes devices and FPGA devices. Si510/511 single-frequency XO is priced from $2.10 to $3.69 (in 10,000-unit quantities). Pricing for the Si514 I2C-programmable XO is $2.71 to $10.23 (in 10,000-unit quantities). Silicon Labs&#8217; Si51x XO/VCXO family is ideal for networking, communications, storage, server, embedded computing and broadcast video systems.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/voltage-controlled/">Silicon Laboratories Si51x XO and VCXO Crystal Oscillators</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/voltage-controlled/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/voltage-controlled/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<title>FPGA-based Prototyping Methodology Manual by Synopsys and Xilinx</title>
		<link>http://fpgablog.com/posts/fpmm-book/</link>
		<comments>http://fpgablog.com/posts/fpmm-book/#comments</comments>
		<pubDate>Wed, 02 Mar 2011 21:05:17 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Other]]></category>
		<category><![CDATA[book]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[FPMM]]></category>
		<category><![CDATA[Methodology Manual]]></category>
		<category><![CDATA[Prototyping]]></category>
		<category><![CDATA[SoC Designs]]></category>
		<category><![CDATA[Synopsys]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=2904</guid>
		<description><![CDATA[Synopsys and Xilinx teamed on the FPGA-based Prototyping Methodology Manual (FPMM): Best Practices in Design-for-Prototyping. The manual covers all aspects of FPGA-based prototyping, including understanding the challenges and benefits of prototyping, the implementation of a SoC design in FPGA, and its use for software and system validation. FPMM is a practical guide to using FPGAs [...]]]></description>
			<content:encoded><![CDATA[<p>Synopsys and Xilinx teamed on the <a href="http://www.amazon.com/gp/product/B004Q9TIJU?ie=UTF8&#038;tag=fpgablog-20&#038;linkCode=as2&#038;camp=1789&#038;creative=390957&#038;creativeASIN=B004Q9TIJU" target="destiny">FPGA-based Prototyping Methodology Manual (FPMM): Best Practices in Design-for-Prototyping</a>. The manual covers all aspects of FPGA-based prototyping, including understanding the challenges and benefits of prototyping, the implementation of a SoC design in FPGA, and its use for software and system validation. FPMM is a practical guide to using FPGAs as a platform for system-on-chip (SoC) development. Engineering teams from BBC Research &#038; Development, Design of System on Silicon (DS2), Freescale Semiconductor, LSI, NVIDIA, STMicroelectronics, and Texas Instruments (TI) contributed to the book.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/fpmm-book/">FPGA-based Prototyping Methodology Manual by Synopsys and Xilinx</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/fpmm-book/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/fpmm-book/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<title>The Altera Embedded Initiative</title>
		<link>http://fpgablog.com/posts/arm-intel-mips/</link>
		<comments>http://fpgablog.com/posts/arm-intel-mips/#comments</comments>
		<pubDate>Tue, 12 Oct 2010 21:39:56 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Other]]></category>
		<category><![CDATA[altera]]></category>
		<category><![CDATA[ARM]]></category>
		<category><![CDATA[design flow]]></category>
		<category><![CDATA[Embedded Initiative]]></category>
		<category><![CDATA[embedded systems]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Intel]]></category>
		<category><![CDATA[MIPS]]></category>
		<category><![CDATA[processor]]></category>
		<category><![CDATA[Tool]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=2622</guid>
		<description><![CDATA[Altera introduced their Embedded Initiative, which will give designers a single FPGA design flow based on the Quartus II development software. The design flow features the Qsys system-level integration tool, a common FPGA intellectual property (IP) library, and the ARM Cortex-A9 MPCore and MIPS Technologies MIPS32 embedded processors. The Qsys system-level integration tool leverages FPGA-optimized [...]]]></description>
			<content:encoded><![CDATA[<p>Altera introduced their Embedded Initiative, which will give designers a single FPGA design flow based on the Quartus II development software. The design flow features the Qsys system-level integration tool, a common FPGA intellectual property (IP) library, and the ARM Cortex-A9 MPCore and MIPS Technologies MIPS32 embedded processors. The Qsys system-level integration tool leverages FPGA-optimized network-on-a-chip technology to support a wide variety of industry-standard IP protocols.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/arm-intel-mips/">The Altera Embedded Initiative</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/arm-intel-mips/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/arm-intel-mips/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2010 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<title>RoweBots Unison Ultra Tiny Linux RTOS for Actel SmartFusion FPGA</title>
		<link>http://fpgablog.com/posts/unison-smartfusion/</link>
		<comments>http://fpgablog.com/posts/unison-smartfusion/#comments</comments>
		<pubDate>Fri, 20 Aug 2010 11:01:00 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Other]]></category>
		<category><![CDATA[Actel]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Linux]]></category>
		<category><![CDATA[OS]]></category>
		<category><![CDATA[POSIX]]></category>
		<category><![CDATA[RoweBots]]></category>
		<category><![CDATA[RTOS]]></category>
		<category><![CDATA[SmartFusion]]></category>
		<category><![CDATA[Unison]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=2461</guid>
		<description><![CDATA[The RoweBots Unison ultra tiny Linux compatible OS is now available for Actel SmartFusion devices. Thanks to the partnership, developers now have the option for Linux-based embedded systems when using SmartFusion intelligent mixed signal FPGAs. Unison consists of a set of modular software components that are either free or commercially licensed. All Unison versions are [...]]]></description>
			<content:encoded><![CDATA[<p>The RoweBots Unison ultra tiny Linux compatible OS is now available for Actel SmartFusion devices. Thanks to the partnership, developers now have the option for Linux-based embedded systems when using SmartFusion intelligent mixed signal FPGAs. Unison consists of a set of modular software components that are either free or commercially licensed. All Unison versions are strictly tested with standardized POSIX test suites. Unison includes over 30 demonstration programs that work out of the box in ten minutes with SoftConsole.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/unison-smartfusion/">RoweBots Unison Ultra Tiny Linux RTOS for Actel SmartFusion FPGA</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/unison-smartfusion/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/unison-smartfusion/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2010 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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