Xilinx and Altera recently announced new product launches – Xilinx’s UltraScale ASIC class ICs, and Altera’s Stratix Generation 10. Analysis of the available hardware, tool, and other information on both products shows what might be in store for designers with these new developments.
In situations were ASICs were previously used, designers are now exploring the use of FPGAs and using FPGAs for prototypes. FPGAs have come a long way in recent years, and the advancements in SystemVerilog tool support have made it an excellent tool for FPGA development.
Altera released version 13.0 of their Quartus II software. Quartus II v13 enables designs targeting Stratix V FPGAs to achieve the fastest Fmax of any FPGA in the industry with a two speed-grade advantage over the nearest competitor. Both the Subscription Edition and the free Web Edition of Quartus II software v13.0 are now available for download.
Altera published a white paper that explores an advanced motor drive or inverter application to illustrate how silicon convergence affects real-time design. The technical paper explains how FPGA and SoC devices speed silicon convergence. The latest advancement in SoC integrates an Altera FPGA with an ARM applications processor, plus a rich peripheral processor subsystem. The title of the Altera article is Real-Time Challenges and Opportunities in SoCs.
Synopsys introduced the HAPS-70 Series FPGA-based prototyping systems for system-on-chip (SoC) designs. The HAPS-70 FPGA-based prototyping systems are available now in nine model variants. Capacities range from 12 to 144 million ASIC gates. The series consists of the HAPS-70 S12, HAPS-70 S24, HAPS-70 S36, HAPS-70 S48, HAPS-70 S60, HAPS-70 S72, HAPS-70 S96, HAPS-70 S120 and HAPS-70 S144. The S denotes ASIC Gate count support.
Analog Devices announced their AD9250 dual-channel, 14-bit, 250 MSPS, A/D converter. It supports the JEDEC JESD204B serial output data interface standard. The ADI AD9250 device features a simplified interface that is ideal for next-generation FPGA-based applications in software-defined radio and medical ultrasound. The 250 MSPS AD9250-250 is available now for $131.57. A 170 MSPS pin-compatible version (AD9250-170) is available for $72.49.
Altera announced the production availability of their 40-Gbps Ethernet and 100-Gbps Ethernet intellectual property cores. The cores can be used to create high-performance, low-cost, subsystem IP in Stratix IV and Stratix V FPGAs. Altera’s 40GbE and 100GbE IP cores are compatible with the recently announced Quartus II software v12.0. They are available for download on the Altera website.
CommAgility introduced the AMC-V6L FPGA processing module. The AMC-V6L AdvancedMC module features the Xilinx Virtex-6 FPGA, 256Mbytes of 16-bit DDR3 SDRAM memory, 128Mbytes of Flash memory, dual Gigabit Ethernet, and two SFP+ sockets. The CommAgility AMC-V6L is sampling now. It is priced at less than $2,000 in 1K+ volume. The AMC-V6L FPGA processing module is ideal for wireless, general-purpose FPGA acceleration and I/O processing applications.
Lattice Semiconductor has adopted the MIPI Battery Interface (BIF) standard within the iCE40 mobileFPGA family of products. As an industry-created and adopted standard, the MIPI BIF single-wire specification accelerates the design and use of smart batteries in mobile devices. Lattice Semiconductor is engaged with key customers on the MIPI BIF standard. They plan to make support broadly available through its IP suite during the first half of this year. The MIPI BIF solutions will be free of charge to customers with high-volume mobile applications.
Altera created a single-chip, dual 100G transponder solution that is implemented in a 28nm high-performance Stratix V FPGA. With the new dual 100G transponder solution, Altera is now able to deliver density that is unachievable with current solutions and puts them on the path to support data rates of 400G and beyond. Altera is currently shipping 28-nm Stratix V FPGAs and OTN IP.