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	<title>FPGA Blog &#187; FPGA-based Product</title>
	<atom:link href="http://fpgablog.com/posts/category/fpga-powered/feed/" rel="self" type="application/rss+xml" />
	<link>http://fpgablog.com</link>
	<description>FPGA (field programmable gate array) and structured ASIC information</description>
	<lastBuildDate>Thu, 09 Feb 2012 18:23:16 +0000</lastBuildDate>
	<language>en</language>
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		<title>HuMANDATA XP68-03-LX45PLCC FPGA Module</title>
		<link>http://fpgablog.com/posts/xilinx-plcc68/</link>
		<comments>http://fpgablog.com/posts/xilinx-plcc68/#comments</comments>
		<pubDate>Thu, 09 Feb 2012 18:23:16 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA-based Product]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[HuMANDATA]]></category>
		<category><![CDATA[LX45]]></category>
		<category><![CDATA[module]]></category>
		<category><![CDATA[PLCC68]]></category>
		<category><![CDATA[Spartan-6]]></category>
		<category><![CDATA[Xilinx]]></category>
		<category><![CDATA[XP68-03-LX45PLCC]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3644</guid>
		<description><![CDATA[HuMANDATA introduced the XP68-03-LX45PLCC FPGA module. The XP68-03-LX45PLCC features the Xilinx Spartan-6 FPGA (XC6SLX45-2CSG324C), 50 user I/Os, on-board 50MHz oscillator, two user LEDs, a user switch, on-board 1.2V regulator and a Power-on Reset IC. The Xilinx PLCC68 Spartan-6 LX45 FPGA module can be equipped on a universal board by using a 68-pin DIP PLCC socket. [...]]]></description>
			<content:encoded><![CDATA[<p>HuMANDATA introduced the XP68-03-LX45PLCC FPGA module. The XP68-03-LX45PLCC features the Xilinx Spartan-6 FPGA (XC6SLX45-2CSG324C), 50 user I/Os, on-board 50MHz oscillator, two user LEDs, a user switch, on-board 1.2V regulator and a Power-on Reset IC. The Xilinx PLCC68 Spartan-6 LX45 FPGA module can be equipped on a universal board by using a 68-pin DIP PLCC socket. The HuMANDATA XP68-03-LX45PLCC module is compliant with the RoHS Directive and is designed for lead-free soldering. It measures only 25.3mm x 25.3mm.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/xilinx-plcc68/">HuMANDATA XP68-03-LX45PLCC FPGA Module</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/xilinx-plcc68/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/xilinx-plcc68/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		</item>
		<item>
		<title>Xilinx Targets 3D and 4K2K Displays with Reference Designs and ACDC Baseboard</title>
		<link>http://fpgablog.com/posts/inrevium-kintex-7/</link>
		<comments>http://fpgablog.com/posts/inrevium-kintex-7/#comments</comments>
		<pubDate>Thu, 05 Jan 2012 16:46:14 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA-based Product]]></category>
		<category><![CDATA[Reference Design]]></category>
		<category><![CDATA[Tool]]></category>
		<category><![CDATA[3D]]></category>
		<category><![CDATA[4K2K]]></category>
		<category><![CDATA[4K2K Mosaic]]></category>
		<category><![CDATA[ACDC]]></category>
		<category><![CDATA[Baseboard]]></category>
		<category><![CDATA[Displays]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[HDTV-to-4K2K]]></category>
		<category><![CDATA[Inrevium]]></category>
		<category><![CDATA[Kintex-7]]></category>
		<category><![CDATA[reference designs]]></category>
		<category><![CDATA[up-converter]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3577</guid>
		<description><![CDATA[Xilinx introduced reference designs and a development baseboard for speeding the development of next-generation, 3D and 4K2K display technologies. The 4K2K Mosaic and HDTV-to-4K2K up-converter targeted reference designs are based on the new 28nm Kintex-7 Field Programmable Gate Array (FPGA). The new ACDC (Acquisition, Contribution, Distribution and Consumption) 1.0 Baseboard also uses Kintex-7 FPGA devices. [...]]]></description>
			<content:encoded><![CDATA[<p>Xilinx introduced reference designs and a development baseboard for speeding the development of next-generation, 3D and 4K2K display technologies. The 4K2K Mosaic and HDTV-to-4K2K up-converter targeted reference designs are based on the new 28nm Kintex-7 Field Programmable Gate Array (FPGA). The new ACDC (Acquisition, Contribution, Distribution and Consumption) 1.0 Baseboard also uses Kintex-7 FPGA devices. The targeted reference designs and ACDC 1.0 Baseboard with the Kintex-7 FPGA will be available in Q2 2012.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/inrevium-kintex-7/">Xilinx Targets 3D and 4K2K Displays with Reference Designs and ACDC Baseboard</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/inrevium-kintex-7/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/inrevium-kintex-7/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		</item>
		<item>
		<title>Innovative Integration Unveils PEX6-COP FPGA Co-processor Card</title>
		<link>http://fpgablog.com/posts/xilinx-pex6cop/</link>
		<comments>http://fpgablog.com/posts/xilinx-pex6cop/#comments</comments>
		<pubDate>Thu, 08 Dec 2011 16:43:41 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA-based Product]]></category>
		<category><![CDATA[Card]]></category>
		<category><![CDATA[Co-processor]]></category>
		<category><![CDATA[FMC]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Innovative Integration]]></category>
		<category><![CDATA[PCI Express]]></category>
		<category><![CDATA[PEX6-COP]]></category>
		<category><![CDATA[Virtex-6]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3535</guid>
		<description><![CDATA[Innovative Integration introduced their PEX6-COP FPGA co-processor card. The flexible board features an integrated FPGA computing core with an industry-standard FMC IO module on a half-length PCI Express desktop or server card. The FPGA computing core supports the Xilinx Virtex 6 FPGA family in densities up to LX550 and SX475. The SX475 offers over 2000 [...]]]></description>
			<content:encoded><![CDATA[<p>Innovative Integration introduced their PEX6-COP FPGA co-processor card. The flexible board features an integrated FPGA computing core with an industry-standard FMC IO module on a half-length PCI Express desktop or server card. The FPGA computing core supports the Xilinx Virtex 6 FPGA family in densities up to LX550 and SX475. The SX475 offers over 2000 DSP MAC elements operating at up to 500 MHz. The FPGA core has two 9MB QDRII+ SRAM banks, two 256MB LPDDR2 DRAM banks, and a 128MB DDR3 bank. Each memory is directly connected to the FPGA and is fully independent.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/xilinx-pex6cop/">Innovative Integration Unveils PEX6-COP FPGA Co-processor Card</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/xilinx-pex6cop/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/xilinx-pex6cop/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		</item>
		<item>
		<title>Microsemi Offers Private Label Program for SmartFusion cSoC and FPGA</title>
		<link>http://fpgablog.com/posts/asic-assp/</link>
		<comments>http://fpgablog.com/posts/asic-assp/#comments</comments>
		<pubDate>Wed, 07 Dec 2011 16:17:39 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA-based Product]]></category>
		<category><![CDATA[ASIC]]></category>
		<category><![CDATA[ASSP]]></category>
		<category><![CDATA[cSoC]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Microsemi]]></category>
		<category><![CDATA[Private Label Program]]></category>
		<category><![CDATA[SmartFusion]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3523</guid>
		<description><![CDATA[Microsemi announced a private labeling program for their SmartFusion customizable system-on-chip (cSoC), and flash and antifuse-based FPGA solutions. Microsemi&#8217;s new private label program enables companies to rapidly deliver economical and differentiated system-on-chip solutions. With the company&#8217;s SmartFusion cSoC devices, engineers can reduce the size of their circuit boards and the external bill-of-material component count while [...]]]></description>
			<content:encoded><![CDATA[<p>Microsemi announced a private labeling program for their SmartFusion customizable system-on-chip (cSoC), and flash and antifuse-based FPGA solutions. Microsemi&#8217;s new private label program enables companies to rapidly deliver economical and differentiated system-on-chip solutions. With the company&#8217;s SmartFusion cSoC devices, engineers can reduce the size of their circuit boards and the external bill-of-material component count while at the same time increasing the mean time between failure.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/asic-assp/">Microsemi Offers Private Label Program for SmartFusion cSoC and FPGA</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/asic-assp/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/asic-assp/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>Trenz Electronic TE0630 Series of FPGA Modules</title>
		<link>http://fpgablog.com/posts/xilinx-micro-module/</link>
		<comments>http://fpgablog.com/posts/xilinx-micro-module/#comments</comments>
		<pubDate>Wed, 30 Nov 2011 19:36:53 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA-based Product]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[micro-module]]></category>
		<category><![CDATA[Spartan-6]]></category>
		<category><![CDATA[TE0630]]></category>
		<category><![CDATA[Trenz Electronic]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3510</guid>
		<description><![CDATA[Trenz Electronic introduced their TE0630 family of FPGA-based industrial micro-modules. The TE0630 features a Xilinx Spartan-6 FPGA, mini-USB 2.0 device port, 1 Gbit (128-Mbyte) DDR3 SDRAM with 16-bit width, 8 Mbyte Flash memory for configuration and operation, and switch-mode power supplies for all on-board voltages. The Trenz TE0630 board is available in different options. It [...]]]></description>
			<content:encoded><![CDATA[<p>Trenz Electronic introduced their TE0630 family of FPGA-based industrial micro-modules. The TE0630 features a Xilinx Spartan-6 FPGA, mini-USB 2.0 device port, 1 Gbit (128-Mbyte) DDR3 SDRAM with 16-bit width, 8 Mbyte Flash memory for configuration and operation, and switch-mode power supplies for all on-board voltages. The Trenz TE0630 board is available in different options. It is ideal for harsh environments and pervasive deployment.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/xilinx-micro-module/">Trenz Electronic TE0630 Series of FPGA Modules</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/xilinx-micro-module/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/xilinx-micro-module/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>Sercos III Real-time Ethernet Solution Features LatticeECP3-35 FPGA</title>
		<link>http://fpgablog.com/posts/automata-lattice/</link>
		<comments>http://fpgablog.com/posts/automata-lattice/#comments</comments>
		<pubDate>Tue, 29 Nov 2011 18:30:04 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA-based Product]]></category>
		<category><![CDATA[AUTOMATA]]></category>
		<category><![CDATA[Ethernet]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[industrial]]></category>
		<category><![CDATA[Lattice Semiconductor]]></category>
		<category><![CDATA[LatticeECP3-35]]></category>
		<category><![CDATA[Networking]]></category>
		<category><![CDATA[Real-time]]></category>
		<category><![CDATA[Sercos III]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3506</guid>
		<description><![CDATA[Lattice Semiconductor recently introduced their Sercos III real-time Ethernet solution. The Sercos III solution features the Lattice FPGA device. It is a low cost, low power FPGA-based alternative for engineers who need to implement flexible industrial networking solutions. Sercos is a digital bus that interconnects motion controls, drives, I/O, sensors and actuators for numerically controlled [...]]]></description>
			<content:encoded><![CDATA[<p>Lattice Semiconductor recently introduced their Sercos III real-time Ethernet solution. The Sercos III solution features the Lattice FPGA device. It is a low cost, low power FPGA-based alternative for engineers who need to implement flexible industrial networking solutions. Sercos is a digital bus that interconnects motion controls, drives, I/O, sensors and actuators for numerically controlled machines and systems. It is designed for the high-speed serial communication of standardized closed-loop real-time data over Industrial Ethernet.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/automata-lattice/">Sercos III Real-time Ethernet Solution Features LatticeECP3-35 FPGA</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/automata-lattice/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/automata-lattice/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>Altera Stratix IV FPGAs Accelerate Novo-G Reconfigurable Supercomputer</title>
		<link>http://fpgablog.com/posts/chrec-fpga/</link>
		<comments>http://fpgablog.com/posts/chrec-fpga/#comments</comments>
		<pubDate>Fri, 18 Nov 2011 16:36:05 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA-based Product]]></category>
		<category><![CDATA[altera]]></category>
		<category><![CDATA[CHREC]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[High-Performance Reconfigurable Computing]]></category>
		<category><![CDATA[Novo-G]]></category>
		<category><![CDATA[Reconfigurable Supercomputer]]></category>
		<category><![CDATA[Stratix IV]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3462</guid>
		<description><![CDATA[The Center for High-Performance Reconfigurable Computing (CHREC) updated their Novo-G supercomputer with Altera Stratix IV FPGA devices. As a result, CHREC increased the system memory and acceleration of the world&#8217;s most powerful supercomputer by a factor of two. CHREC was able to realize a greater performance-to-cost ratio with modest increases in size, power and cooling. [...]]]></description>
			<content:encoded><![CDATA[<p>The Center for High-Performance Reconfigurable Computing (CHREC) updated their Novo-G supercomputer with Altera Stratix IV FPGA devices. As a result, CHREC increased the system memory and acceleration of the world&#8217;s most powerful supercomputer by a factor of two. CHREC was able to realize a greater performance-to-cost ratio with modest increases in size, power and cooling.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/chrec-fpga/">Altera Stratix IV FPGAs Accelerate Novo-G Reconfigurable Supercomputer</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/chrec-fpga/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/chrec-fpga/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<title>TEK Microsystems Gemini-V6 FPGA-based Processing Solution</title>
		<link>http://fpgablog.com/posts/xilinx-adc-dac/</link>
		<comments>http://fpgablog.com/posts/xilinx-adc-dac/#comments</comments>
		<pubDate>Tue, 15 Nov 2011 07:39:23 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA-based Product]]></category>
		<category><![CDATA[ADC]]></category>
		<category><![CDATA[ADC12D1800RF]]></category>
		<category><![CDATA[DAC]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Gemini-V6]]></category>
		<category><![CDATA[National Semiconductor]]></category>
		<category><![CDATA[Processing Solution]]></category>
		<category><![CDATA[QuiXilica]]></category>
		<category><![CDATA[TEK Microsystems]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3469</guid>
		<description><![CDATA[TEK Microsystems introduced the Gemini-V6 FPGA-based processing solution. The Gemini-V6 features two front end FPGA devices. One front end attaches to the ADCs and other front end attaches to the 4 GHz DAC. The front end FPGAs can be configured with Xilinx LX240, SX315, or SX475 devices. The TEK Gemini-V6 is a member of the [...]]]></description>
			<content:encoded><![CDATA[<p>TEK Microsystems introduced the Gemini-V6 FPGA-based processing solution. The Gemini-V6 features two front end FPGA devices. One front end attaches to the ADCs and other front end attaches to the 4 GHz DAC. The front end FPGAs can be configured with Xilinx LX240, SX315, or SX475 devices. The TEK Gemini-V6 is a member of the QuiXilica family, and is based on the National Semiconductor ADC12D1800RF device. The Gemini-V6 will be available in January 2012.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/xilinx-adc-dac/">TEK Microsystems Gemini-V6 FPGA-based Processing Solution</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/xilinx-adc-dac/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/xilinx-adc-dac/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<title>TEK Microsystems QuiXilica Calypso-V6 Digitizer</title>
		<link>http://fpgablog.com/posts/adc-fpga/</link>
		<comments>http://fpgablog.com/posts/adc-fpga/#comments</comments>
		<pubDate>Wed, 09 Nov 2011 16:36:33 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA-based Product]]></category>
		<category><![CDATA[ADC]]></category>
		<category><![CDATA[Calypso-V6]]></category>
		<category><![CDATA[Digitizer]]></category>
		<category><![CDATA[FPGA Processing]]></category>
		<category><![CDATA[QuiXilica]]></category>
		<category><![CDATA[TEK Microsystems]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3451</guid>
		<description><![CDATA[TEK Microsystems introduced their QuiXilica Calypso-V6 digitizer. The Calypso-V6 features four separate ADC devices, with each pair of devices assigned to its own front end FPGA for signal processing. The front end FPGAs can be configured with LX240, SX315, or SX475 devices. The new QuiXilica digitizer offers the highest FPGA processing density available in any [...]]]></description>
			<content:encoded><![CDATA[<p>TEK Microsystems introduced their QuiXilica Calypso-V6 digitizer. The Calypso-V6 features four separate ADC devices, with each pair of devices assigned to its own front end FPGA for signal processing. The front end FPGAs can be configured with LX240, SX315, or SX475 devices. The new QuiXilica digitizer offers the highest FPGA processing density available in any 6U form factor. It is also the only VME / VXS platform that supports Virtex-6 FPGA devices. The TEK Calypso-V6 will be available in January 2011.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/adc-fpga/">TEK Microsystems QuiXilica Calypso-V6 Digitizer</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/adc-fpga/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/adc-fpga/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<title>Nallatech PCIe-287N Xilinx 7 Series FPGA Network Processing Card</title>
		<link>http://fpgablog.com/posts/intel-pcie287n/</link>
		<comments>http://fpgablog.com/posts/intel-pcie287n/#comments</comments>
		<pubDate>Mon, 07 Nov 2011 13:54:29 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA-based Product]]></category>
		<category><![CDATA[7 Series FPGA]]></category>
		<category><![CDATA[Nallatech]]></category>
		<category><![CDATA[Network Processing Card]]></category>
		<category><![CDATA[PCIe-287N]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3437</guid>
		<description><![CDATA[Nallatech introduced their PCIe-287N network processing card. The PCIe-287N features two user-accessible Kintex-7 FPGA devices directly coupled to four SFP+ ports. Each FPGA utilizes multiple independent banks of high-bandwidth, QDR-II+ SRAM and DDR3 SDRAM to support random access and deep storage. A third, dedicated FPGA facilitates an 8-lane, PCIe Gen 2, host interface supporting sustained [...]]]></description>
			<content:encoded><![CDATA[<p>Nallatech introduced their PCIe-287N network processing card. The PCIe-287N features two user-accessible Kintex-7 FPGA devices directly coupled to four SFP+ ports. Each FPGA utilizes multiple independent banks of high-bandwidth, QDR-II+ SRAM and DDR3 SDRAM to support random access and deep storage. A third, dedicated FPGA facilitates an 8-lane, PCIe Gen 2, host interface supporting sustained bandwidths up to 5GBytes/sec.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/intel-pcie287n/">Nallatech PCIe-287N Xilinx 7 Series FPGA Network Processing Card</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/intel-pcie287n/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/intel-pcie287n/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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