<?xml version="1.0" encoding="UTF-8"?>
<rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:wfw="http://wellformedweb.org/CommentAPI/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	xmlns:sy="http://purl.org/rss/1.0/modules/syndication/"
	xmlns:slash="http://purl.org/rss/1.0/modules/slash/"
	>

<channel>
	<title>FPGA Blog &#187; FPGA</title>
	<atom:link href="http://fpgablog.com/posts/category/field-programmable-gate-array/feed/" rel="self" type="application/rss+xml" />
	<link>http://fpgablog.com</link>
	<description>FPGA (field programmable gate array) and structured ASIC information</description>
	<lastBuildDate>Thu, 09 Feb 2012 18:23:16 +0000</lastBuildDate>
	<language>en</language>
	<sy:updatePeriod>hourly</sy:updatePeriod>
	<sy:updateFrequency>1</sy:updateFrequency>
	<generator>http://wordpress.org/?v=3.3</generator>
		<item>
		<title>LatticeECP3 FPGA Devices in Low Power, High Speed, and Small Packages</title>
		<link>http://fpgablog.com/posts/lattice-semiconductor-latticeecp3/</link>
		<comments>http://fpgablog.com/posts/lattice-semiconductor-latticeecp3/#comments</comments>
		<pubDate>Tue, 24 Jan 2012 17:44:16 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[High-Speed]]></category>
		<category><![CDATA[Lattice Semiconductor]]></category>
		<category><![CDATA[LatticeECP3]]></category>
		<category><![CDATA[Low-Power]]></category>
		<category><![CDATA[Small Packages]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3598</guid>
		<description><![CDATA[Lattice Semiconductor Corporation is offering low power, high speed, and small form-factor versions of their LatticeECP3 FPGA devices. The new packaging helps engineers create power and space limited applications in professional cameras, surveillance cameras, medical imaging, video communication, and small-form-factor wireline and wireless appliances. Prices for the LatticeECP3-17K Mini Device in 328csBGA package start at [...]]]></description>
			<content:encoded><![CDATA[<p>Lattice Semiconductor Corporation is offering low power, high speed, and small form-factor versions of their LatticeECP3 FPGA devices. The new packaging helps engineers create power and space limited applications in professional cameras, surveillance cameras, medical imaging, video communication, and small-form-factor wireline and wireless appliances. Prices for the LatticeECP3-17K Mini Device in 328csBGA package start at $4.95 (in 500K unit volume). Delivery will be in the fourth quarter of 2013.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/lattice-semiconductor-latticeecp3/">LatticeECP3 FPGA Devices in Low Power, High Speed, and Small Packages</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/lattice-semiconductor-latticeecp3/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/lattice-semiconductor-latticeecp3/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
			<wfw:commentRss>http://fpgablog.com/posts/lattice-semiconductor-latticeecp3/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Lattice Semiconductor Acquires SiliconBlue Technologies for $62 Million</title>
		<link>http://fpgablog.com/posts/custom-mobile-device/</link>
		<comments>http://fpgablog.com/posts/custom-mobile-device/#comments</comments>
		<pubDate>Tue, 13 Dec 2011 07:11:45 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[custom mobile device]]></category>
		<category><![CDATA[Handheld]]></category>
		<category><![CDATA[Lattice Semiconductor]]></category>
		<category><![CDATA[Mobile Consumer]]></category>
		<category><![CDATA[mobileFPGA]]></category>
		<category><![CDATA[SiliconBlue Technologies]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3550</guid>
		<description><![CDATA[Lattice Semiconductor will acquire SiliconBlue Technologies for about $62 million in cash. According to Lattice, the acquisition of SiliconBlue is aligned with their strategic long range plan and will help accelerate their growth strategy in the mobile consumer market. Silicon Blue will further strengthen Lattice&#8217;s product roadmap by adding a scalable, low cost, low power [...]]]></description>
			<content:encoded><![CDATA[<p>Lattice Semiconductor will acquire SiliconBlue Technologies for about $62 million in cash. According to Lattice, the acquisition of SiliconBlue is aligned with their strategic long range plan and will help accelerate their growth strategy in the mobile consumer market. Silicon Blue will further strengthen Lattice&#8217;s product roadmap by adding a scalable, low cost, low power nonvolatile memory FPGA, along with key personnel and blue chip customers.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/custom-mobile-device/">Lattice Semiconductor Acquires SiliconBlue Technologies for $62 Million</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/custom-mobile-device/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/custom-mobile-device/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
			<wfw:commentRss>http://fpgablog.com/posts/custom-mobile-device/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>LatticeECP4 FPGA Family</title>
		<link>http://fpgablog.com/posts/latticeecp4-fpga/</link>
		<comments>http://fpgablog.com/posts/latticeecp4-fpga/#comments</comments>
		<pubDate>Mon, 28 Nov 2011 18:18:39 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[6G SERDES]]></category>
		<category><![CDATA[Communication Engines]]></category>
		<category><![CDATA[DSP Blocks]]></category>
		<category><![CDATA[Lattice Semiconductor]]></category>
		<category><![CDATA[LatticeECP4]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3499</guid>
		<description><![CDATA[Lattice Semiconductor introduced their LatticeECP4 FPGA family. The next generation FPGA devices feature 6 Gbps SERDES, low cost wire-bond packages, powerful DSP Blocks and hard IP-based Communication Engines for cost- and power-sensitive wireless, wireline, video and computing applications. Samples of the LatticeECP4 devices will be available in the first half of 2012 and high-volume production [...]]]></description>
			<content:encoded><![CDATA[<p>Lattice Semiconductor introduced their LatticeECP4 FPGA family. The next generation FPGA devices feature 6 Gbps SERDES, low cost wire-bond packages, powerful DSP Blocks and hard IP-based Communication Engines for cost- and power-sensitive wireless, wireline, video and computing applications. Samples of the LatticeECP4 devices will be available in the first half of 2012 and high-volume production delivery is scheduled for the second half of 2012. The LatticeECP4 FPGAs are ideal for remote wireless radio heads, distributed antenna systems, cellular basestations, ethernet aggregation, switching, routing, industrial networking, video signal processing, video transmission and data center computing.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/latticeecp4-fpga/">LatticeECP4 FPGA Family</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/latticeecp4-fpga/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/latticeecp4-fpga/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
			<wfw:commentRss>http://fpgablog.com/posts/latticeecp4-fpga/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>White Paper: Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs</title>
		<link>http://fpgablog.com/posts/100g-article/</link>
		<comments>http://fpgablog.com/posts/100g-article/#comments</comments>
		<pubDate>Wed, 26 Oct 2011 15:53:07 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[FPGA-based Product]]></category>
		<category><![CDATA[100-GbE]]></category>
		<category><![CDATA[100G]]></category>
		<category><![CDATA[altera]]></category>
		<category><![CDATA[Stratix V]]></category>
		<category><![CDATA[White Paper]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3394</guid>
		<description><![CDATA[Altera published a white paper about how Altera FPGA devices are addressing 100-GbE line card design challenges. As various standard bodies finalize the 100G standards for transport, Ethernet, and optical interfaces, FPGAs play a vital role for early adopters of technology who want to design 100G production systems. As a result of increasing demand for [...]]]></description>
			<content:encoded><![CDATA[<p>Altera published a white paper about how Altera FPGA devices are addressing 100-GbE line card design challenges. As various standard bodies finalize the 100G standards for transport, Ethernet, and optical interfaces, FPGAs play a vital role for early adopters of technology who want to design 100G production systems. As a result of increasing demand for more bandwidth, service providers are looking at emerging 40-GbE/100-GbE standards for their next-generation line card options. Altera Stratix V FPGAs solve the bandwidth problem by providing integrated 12.5-Gbps transceivers with hardened 100G PCS functions on the 28nm technology node.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/100g-article/">White Paper: Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/100g-article/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/100g-article/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
			<wfw:commentRss>http://fpgablog.com/posts/100g-article/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Highest Capacity FPGA: Xilinx Virtex-7 2000T Field Programmable Gate Array</title>
		<link>http://fpgablog.com/posts/stacked-silicon/</link>
		<comments>http://fpgablog.com/posts/stacked-silicon/#comments</comments>
		<pubDate>Tue, 25 Oct 2011 17:16:19 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[2.5-D]]></category>
		<category><![CDATA[2.5D]]></category>
		<category><![CDATA[IC stacking]]></category>
		<category><![CDATA[SSI]]></category>
		<category><![CDATA[Stacked Silicon Interconnect]]></category>
		<category><![CDATA[Virtex-7 2000T]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3390</guid>
		<description><![CDATA[The Xilinx Virtex-7 2000T Field Programmable Gate Array is the highest-capacity programmable logic device. The Virtex-7 2000T FPGA features two million logic cells, 6.8 billion transistors, 12.5Gb/s serial transceivers, and 2.5D Stacked Silicon Interconnect (SSI) technology. 2.5-D IC stacking results in capacities that otherwise wouldn&#8217;t be possible in an FPGA for at least another process [...]]]></description>
			<content:encoded><![CDATA[<p>The Xilinx Virtex-7 2000T Field Programmable Gate Array is the highest-capacity programmable logic device. The Virtex-7 2000T FPGA features two million logic cells, 6.8 billion transistors, 12.5Gb/s serial transceivers, and 2.5D Stacked Silicon Interconnect (SSI) technology. 2.5-D IC stacking results in capacities that otherwise wouldn&#8217;t be possible in an FPGA for at least another process generation. Initial engineering samples of Virtex-7 2000T FPGA devices are shipping now.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/stacked-silicon/">Highest Capacity FPGA: Xilinx Virtex-7 2000T Field Programmable Gate Array</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/stacked-silicon/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/stacked-silicon/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
			<wfw:commentRss>http://fpgablog.com/posts/stacked-silicon/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Altera Cyclone V and Arria V SoC FPGA Families</title>
		<link>http://fpgablog.com/posts/arm-cyclone-arria-5/</link>
		<comments>http://fpgablog.com/posts/arm-cyclone-arria-5/#comments</comments>
		<pubDate>Tue, 11 Oct 2011 17:17:08 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[altera]]></category>
		<category><![CDATA[ARM Processor]]></category>
		<category><![CDATA[Arria V]]></category>
		<category><![CDATA[Cyclone V]]></category>
		<category><![CDATA[field programmable gate arrays]]></category>
		<category><![CDATA[SoC FPGAs]]></category>
		<category><![CDATA[System-on-Chip]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3346</guid>
		<description><![CDATA[Altera launched their new ARM-based SoC FPGA family. The devices feature 28nm Cyclone V and Arria V FPGA fabric, dual-core ARM Cortex-A9 MPCore processor, error correcting code (ECC) protected memory controllers, peripherals and high-bandwidth interconnect on a single chip. Altera&#8217;s Cyclone V and Arria V SoC FPGA silicon will be available in the second half [...]]]></description>
			<content:encoded><![CDATA[<p>Altera launched their new ARM-based SoC FPGA family. The devices feature 28nm Cyclone V and Arria V FPGA fabric, dual-core ARM Cortex-A9 MPCore processor, error correcting code (ECC) protected memory controllers, peripherals and high-bandwidth interconnect on a single chip. Altera&#8217;s Cyclone V and Arria V SoC FPGA silicon will be available in the second half of next year. Prices of the new system-on-chip field programmable gate arrays start at less than $15.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/arm-cyclone-arria-5/">Altera Cyclone V and Arria V SoC FPGA Families</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/arm-cyclone-arria-5/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/arm-cyclone-arria-5/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
			<wfw:commentRss>http://fpgablog.com/posts/arm-cyclone-arria-5/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Xilinx Radiation Hardened Virtex-5QV FPGA Ready fo Space</title>
		<link>http://fpgablog.com/posts/afrl-fpga/</link>
		<comments>http://fpgablog.com/posts/afrl-fpga/#comments</comments>
		<pubDate>Thu, 21 Jul 2011 17:56:23 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[AFRL]]></category>
		<category><![CDATA[Mega-Rad]]></category>
		<category><![CDATA[Radiation Hardened]]></category>
		<category><![CDATA[Reconfigurable FPGAs]]></category>
		<category><![CDATA[Space-Grade]]></category>
		<category><![CDATA[Virtex-5QV]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3235</guid>
		<description><![CDATA[Xilinx&#8217;s radiation-hardened space-grade Virtex-5QV FPGA is available in production with greater than 1Mrad(Si) Total Ionizing Dose (TID) capabilities. The radiation-hardened version of the commercial Xilinx Virtex-5 FPGA was developed under sponsorship by AFRL&#8217;s Space Vehicles Directorate. The FPGA is the first of its kind reprogrammable Single-Event-Upset (SEU) hardened FPGA specifically designed to withstand the harshest [...]]]></description>
			<content:encoded><![CDATA[<p>Xilinx&#8217;s radiation-hardened space-grade Virtex-5QV FPGA is available in production with greater than 1Mrad(Si) Total Ionizing Dose (TID) capabilities. The radiation-hardened version of the commercial Xilinx Virtex-5 FPGA was developed under sponsorship by AFRL&#8217;s Space Vehicles Directorate. The FPGA is the first of its kind reprogrammable Single-Event-Upset (SEU) hardened FPGA specifically designed to withstand the harshest radiation environments. It supports the broadest range of space borne missions from low-earth orbit and beyond.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/afrl-fpga/">Xilinx Radiation Hardened Virtex-5QV FPGA Ready fo Space</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/afrl-fpga/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/afrl-fpga/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
			<wfw:commentRss>http://fpgablog.com/posts/afrl-fpga/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Lattice PCI Express 2.0 Solution</title>
		<link>http://fpgablog.com/posts/trellisys-pcie/</link>
		<comments>http://fpgablog.com/posts/trellisys-pcie/#comments</comments>
		<pubDate>Tue, 05 Jul 2011 17:03:56 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[IP Core]]></category>
		<category><![CDATA[BFM]]></category>
		<category><![CDATA[Bus Functional Model]]></category>
		<category><![CDATA[LatticeECP3]]></category>
		<category><![CDATA[PCI Express]]></category>
		<category><![CDATA[PCIe]]></category>
		<category><![CDATA[Trellisys]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3209</guid>
		<description><![CDATA[According to Lattice Semiconductor, their solution is interoperable with existing PCIe 2.0 supported systems. At a recent PCI-SIG workshop, the LatticeECP3 FPGA and its PCI Express (PCIe) IP core passed PCI-SIG PCIe v2.0 compliance and interoperability testing for 1- and 4-lane configurations. As a result, the LatticeECP3 FPGA family is now compliant with the PCI [...]]]></description>
			<content:encoded><![CDATA[<p>According to Lattice Semiconductor, their solution is interoperable with existing PCIe 2.0 supported systems. At a recent PCI-SIG workshop, the LatticeECP3 FPGA and its PCI Express (PCIe) IP core passed PCI-SIG PCIe v2.0 compliance and interoperability testing for 1- and 4-lane configurations. As a result, the LatticeECP3 FPGA family is now compliant with the PCI Express 2.0 specification at 2.5Gbps. Lattice also worked with Trellisys on a PCIe Bus Functional Model (BFM) for Lattice&#8217;s PCI Express x1 and x4 IP Cores.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/trellisys-pcie/">Lattice PCI Express 2.0 Solution</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/trellisys-pcie/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/trellisys-pcie/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
			<wfw:commentRss>http://fpgablog.com/posts/trellisys-pcie/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Altera 28nm Stratix V FPGA Features Most Transistors on an IC</title>
		<link>http://fpgablog.com/posts/stratix-5-transistors/</link>
		<comments>http://fpgablog.com/posts/stratix-5-transistors/#comments</comments>
		<pubDate>Tue, 19 Apr 2011 14:22:31 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[altera]]></category>
		<category><![CDATA[IC]]></category>
		<category><![CDATA[Integrated Circuit]]></category>
		<category><![CDATA[Stratix V]]></category>
		<category><![CDATA[Transistors]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3030</guid>
		<description><![CDATA[According to Altera, the company has set a record for packing the most transistors onto an integrated circuit. Their 28nm Stratix V FPGAs are the semiconductor industry&#8217;s first devices to feature 3.9 billion transistors. Altera surpassed the known record for transistors when it taped out Stratix V FPGA devices at the end of 2010. Read [...]]]></description>
			<content:encoded><![CDATA[<p>According to Altera, the company has set a record for packing the most transistors onto an integrated circuit. Their 28nm Stratix V FPGAs are the semiconductor industry&#8217;s first devices to feature 3.9 billion transistors. Altera surpassed the known record for transistors when it taped out Stratix V FPGA devices at the end of 2010.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/stratix-5-transistors/">Altera 28nm Stratix V FPGA Features Most Transistors on an IC</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/stratix-5-transistors/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/stratix-5-transistors/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
			<wfw:commentRss>http://fpgablog.com/posts/stratix-5-transistors/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Lattice Semiconductor MachXO2 LCMXO2-1200 PLDs in Production</title>
		<link>http://fpgablog.com/posts/1200ze-1200hc/</link>
		<comments>http://fpgablog.com/posts/1200ze-1200hc/#comments</comments>
		<pubDate>Wed, 06 Apr 2011 14:51:09 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Lattice Semiconductor]]></category>
		<category><![CDATA[LCMXO2-1200]]></category>
		<category><![CDATA[LCMXO2-1200HC]]></category>
		<category><![CDATA[LCMXO2-1200ZE]]></category>
		<category><![CDATA[MachXO2]]></category>
		<category><![CDATA[PLD]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3009</guid>
		<description><![CDATA[The MachXO2 LCMXO2-1200 PLD, from Lattice Semiconductor, has been qualified and released to production. The LCMXO2-1200 is one of six members of the MachXO2 PLD family. MachXO2 LCMXO2-1200 devices are available in both commercial and industrial temperature grade options. The devices are offered in a broad range of low-cost package options including 100-pin TQFP, 144-pin [...]]]></description>
			<content:encoded><![CDATA[<p>The MachXO2 LCMXO2-1200 PLD, from Lattice Semiconductor, has been qualified and released to production. The LCMXO2-1200 is one of six members of the MachXO2 PLD family. MachXO2 LCMXO2-1200 devices are available in both commercial and industrial temperature grade options. The devices are offered in a broad range of low-cost package options including 100-pin TQFP, 144-pin TQFP and 132-pin csBGA. The 256-pin ftBGA and 25-ball WLCSP will be made available during 2011. All device members of the MachXO2 family are expected to be in production by the end of this year.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/1200ze-1200hc/">Lattice Semiconductor MachXO2 LCMXO2-1200 PLDs in Production</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/1200ze-1200hc/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/1200ze-1200hc/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
			<wfw:commentRss>http://fpgablog.com/posts/1200ze-1200hc/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
	</channel>
</rss>

