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	<title>FPGA Blog &#187; FPGA</title>
	<atom:link href="http://fpgablog.com/posts/category/field-programmable-gate-array/feed/" rel="self" type="application/rss+xml" />
	<link>http://fpgablog.com</link>
	<description>FPGA (field programmable gate array) and structured ASIC information</description>
	<lastBuildDate>Tue, 15 May 2012 17:19:14 +0000</lastBuildDate>
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		<title>Lattice Released iCE40 Los Angeles mobileFPGA in Volume Production</title>
		<link>http://fpgablog.com/posts/lp640-lp1k-lp4k-lp8k-hx640-hx1k-hx4k-hx8k/</link>
		<comments>http://fpgablog.com/posts/lp640-lp1k-lp4k-lp8k-hx640-hx1k-hx4k-hx8k/#comments</comments>
		<pubDate>Tue, 15 May 2012 17:19:14 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[HX1K]]></category>
		<category><![CDATA[HX4K]]></category>
		<category><![CDATA[HX640]]></category>
		<category><![CDATA[HX8K]]></category>
		<category><![CDATA[iCE40]]></category>
		<category><![CDATA[Lattice Semiconductor]]></category>
		<category><![CDATA[Los Angeles]]></category>
		<category><![CDATA[LP1K]]></category>
		<category><![CDATA[LP4K]]></category>
		<category><![CDATA[LP640]]></category>
		<category><![CDATA[LP8K]]></category>
		<category><![CDATA[mobileFPGA]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3860</guid>
		<description><![CDATA[Eight devices in the Lattice Semiconductor iCE40 Los Angeles mobileFPGA family have been fully qualified and released into volume production. The low power LP640, LP1K, LP4K and LP8K devices, and the higher performance HX640, HX1K, HX4K and HX8K devices have been production released with 17 different device/package combinations. Read more Lattice Released iCE40 Los Angeles [...]]]></description>
			<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2012/Lattice-iCE40.jpg" width="391" height="240" alt="Lattice Semiconductor's iCE40 Los Angeles mobileFPGA family" border="0" /></p>
<p>Eight devices in the Lattice Semiconductor iCE40 Los Angeles mobileFPGA family have been fully qualified and released into volume production. The low power LP640, LP1K, LP4K and LP8K devices, and the higher performance HX640, HX1K, HX4K and HX8K devices have been production released with 17 different device/package combinations.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/lp640-lp1k-lp4k-lp8k-hx640-hx1k-hx4k-hx8k/">Lattice Released iCE40 Los Angeles mobileFPGA in Volume Production</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/lp640-lp1k-lp4k-lp8k-hx640-hx1k-hx4k-hx8k/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/lp640-lp1k-lp4k-lp8k-hx640-hx1k-hx4k-hx8k/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		</item>
		<item>
		<title>Lattice Introduces New Power Management Architecture, Releases Two App Notes</title>
		<link>http://fpgablog.com/posts/star-topology-power-management/</link>
		<comments>http://fpgablog.com/posts/star-topology-power-management/#comments</comments>
		<pubDate>Mon, 07 May 2012 16:19:36 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[App Notes]]></category>
		<category><![CDATA[Architecture]]></category>
		<category><![CDATA[Lattice Semiconductor]]></category>
		<category><![CDATA[Platform Manager]]></category>
		<category><![CDATA[Power Management]]></category>
		<category><![CDATA[Power Supply]]></category>
		<category><![CDATA[star topology]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3854</guid>
		<description><![CDATA[Lattice Semiconductor introduced a new power management architecture. The new in-system upgradable, star topology power management architecture can be used across a wide range of circuit boards requiring over 12 power supply rails. In addition, Lattice also released two new application notes for their Platform Manager devices that will enable engineers to quickly adopt the [...]]]></description>
			<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2012/Lattice-Power-Management.gif" width="468" height="201" alt="Platform Manager Provides Centralized Sequencing and Monitoring of up to 36 Power Supplies" border="0" /></p>
<p>Lattice Semiconductor introduced a new power management architecture. The new in-system upgradable, star topology power management architecture can be used across a wide range of circuit boards requiring over 12 power supply rails. In addition, Lattice also released two new application notes for their Platform Manager devices that will enable engineers to quickly adopt the new architecture.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/star-topology-power-management/">Lattice Introduces New Power Management Architecture, Releases Two App Notes</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/star-topology-power-management/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/star-topology-power-management/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		</item>
		<item>
		<title>Lattice Semiconductor Packs MachXO2 PLD into 32 QFN Package</title>
		<link>http://fpgablog.com/posts/machxo2-256-qfn/</link>
		<comments>http://fpgablog.com/posts/machxo2-256-qfn/#comments</comments>
		<pubDate>Tue, 01 May 2012 15:52:23 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[32 QFN]]></category>
		<category><![CDATA[Lattice Semiconductor]]></category>
		<category><![CDATA[MachXO2]]></category>
		<category><![CDATA[PLD]]></category>
		<category><![CDATA[Programmable Logic Devices]]></category>
		<category><![CDATA[Quad Flatpack No-leads]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3838</guid>
		<description><![CDATA[Lattice Semiconductor&#8217;s MachXO2 family of programmable logic devices (PLD) is available in a new 32 QFN (Quad Flatpack No-leads) package. Engineering samples of the MachXO2-256 in the 32 QFN package are available now. Production-qualified versions will be available in the third quarter of this year. MachXO2 PLDs with 256 LUTs are priced at $0.55 in [...]]]></description>
			<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2012/Lattice-MachXO2.jpg" width="250" height="250" alt="Lattice Semiconductor MachXO2 Programmable Logic Devices" border="0" /></p>
<p>Lattice Semiconductor&#8217;s MachXO2 family of programmable logic devices (PLD) is available in a new 32 QFN (Quad Flatpack No-leads) package. Engineering samples of the MachXO2-256 in the 32 QFN package are available now. Production-qualified versions will be available in the third quarter of this year. MachXO2 PLDs with 256 LUTs are priced at $0.55 in volumes of 250K units. The programmable devices are supported in Lattice Diamond design software version 1.4.2.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/machxo2-256-qfn/">Lattice Semiconductor Packs MachXO2 PLD into 32 QFN Package</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/machxo2-256-qfn/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/machxo2-256-qfn/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		</item>
		<item>
		<title>Achronix Speedster22i FPGAs Feature High Density and High Performance Versions</title>
		<link>http://fpgablog.com/posts/speedster22i-hd-hp/</link>
		<comments>http://fpgablog.com/posts/speedster22i-hd-hp/#comments</comments>
		<pubDate>Tue, 24 Apr 2012 07:01:19 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[28nm]]></category>
		<category><![CDATA[Achronix Semiconductor]]></category>
		<category><![CDATA[field programmable gate arrays]]></category>
		<category><![CDATA[Intel]]></category>
		<category><![CDATA[Speedster22i]]></category>
		<category><![CDATA[Speedster22i-HD]]></category>
		<category><![CDATA[Speedster22i-HP]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3816</guid>
		<description><![CDATA[Achronix Semiconductor revealed details of their Speedster22i HD and HP Field Programmable Gate Arrays. The Speedster22i-HP FPGA family is optimized for ultra high performance. The Speedster22i-HD FPGA is optimized for high density. The Speedster22i FPGA Platform uses Intel&#8217;s 22nm process technology. Engineering samples of the HD1000 will start shipping in the third quarter of this [...]]]></description>
			<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2012/Achronix-Speedster22i-FPGA.jpg" width="468" height="119" alt="Achronix Semiconductor Speedster22i HD and HP Field Programmable Gate Arrays (FPGA)" border="0" /></p>
<p>Achronix Semiconductor revealed details of their Speedster22i HD and HP Field Programmable Gate Arrays. The Speedster22i-HP FPGA family is optimized for ultra high performance. The Speedster22i-HD FPGA is optimized for high density. The Speedster22i FPGA Platform uses Intel&#8217;s 22nm process technology. Engineering samples of the HD1000 will start shipping in the third quarter of this year. The HD1000 is the world&#8217;s largest FPGA. It features over 1 million effective LUTs and 84 Mb of embedded RAM. The remaining HD and HP FPGA devices will be released in the following 12 months.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/speedster22i-hd-hp/">Achronix Speedster22i FPGAs Feature High Density and High Performance Versions</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/speedster22i-hd-hp/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/speedster22i-hd-hp/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>Xilinx Defense-Grade Virtex-6Q FPGA Includes Anti-Tamper Protection</title>
		<link>http://fpgablog.com/posts/nsa-secmon/</link>
		<comments>http://fpgablog.com/posts/nsa-secmon/#comments</comments>
		<pubDate>Tue, 27 Mar 2012 16:58:22 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[IP Core]]></category>
		<category><![CDATA[Anti-Counterfeit]]></category>
		<category><![CDATA[Anti-Tamper]]></category>
		<category><![CDATA[AT]]></category>
		<category><![CDATA[defense grade]]></category>
		<category><![CDATA[NSA]]></category>
		<category><![CDATA[SECMON]]></category>
		<category><![CDATA[Secure]]></category>
		<category><![CDATA[Security Monitor]]></category>
		<category><![CDATA[Virtex-6Q]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3760</guid>
		<description><![CDATA[The Xilinx Virtex-6Q Field Programmable Gate Array (FPGA) family is a high performance defense-grade, programmable solution for major defense applications. The combination of Virtex-6Q FPGA with the Xilinx Security Monitor (SECMON) IP core provides a secure platform for Aerospace and Defense (A&#038;D) designs used in critical AT applications. The SECMON IP core offers a level [...]]]></description>
			<content:encoded><![CDATA[<p>The Xilinx Virtex-6Q Field Programmable Gate Array (FPGA) family is a high performance defense-grade, programmable solution for major defense applications. The combination of Virtex-6Q FPGA with the Xilinx Security Monitor (SECMON) IP core provides a secure platform for Aerospace and Defense (A&#038;D) designs used in critical AT applications. The SECMON IP core offers a level of Anti-Tamper (AT) protection that will further strengthen the secure capabilities of the Virtex-6Q family of FPGAs.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/nsa-secmon/">Xilinx Defense-Grade Virtex-6Q FPGA Includes Anti-Tamper Protection</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/nsa-secmon/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/nsa-secmon/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>Xilinx Introduces Dual 100 Gbps Gearbox Solution</title>
		<link>http://fpgablog.com/posts/cfp2-optical-modules/</link>
		<comments>http://fpgablog.com/posts/cfp2-optical-modules/#comments</comments>
		<pubDate>Mon, 05 Mar 2012 18:18:26 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[IP Core]]></category>
		<category><![CDATA[28nm]]></category>
		<category><![CDATA[CFP2]]></category>
		<category><![CDATA[Dual 100 Gbps]]></category>
		<category><![CDATA[Gearbox]]></category>
		<category><![CDATA[IP Cores]]></category>
		<category><![CDATA[optical modules]]></category>
		<category><![CDATA[Solution]]></category>
		<category><![CDATA[Virtex-7 HT]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3709</guid>
		<description><![CDATA[Xilinx introduced their dual 100G Gearbox solution, which features a 28nm Virtex-7 HT FPGA and dual 100G Gearbox intellectual property cores. The new Xilinx solution enables equipment vendors to connect 100 Gbps interfaces with up to two CFP2 optical modules while lowering the overall BOM by reducing chip count and allowing integration with OTN framers [...]]]></description>
			<content:encoded><![CDATA[<p>Xilinx introduced their dual 100G Gearbox solution, which features a 28nm Virtex-7 HT FPGA and dual 100G Gearbox intellectual property cores. The new Xilinx solution enables equipment vendors to connect 100 Gbps interfaces with up to two CFP2 optical modules while lowering the overall BOM by reducing chip count and allowing integration with OTN framers as well as 100G bridges into a single chip. The programmability of the Virtex-7 HT FPGA ensures that the equipment vendors can easily keep up with changes in standards that are still evolving in the optical, Ethernet and OTN market space.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/cfp2-optical-modules/">Xilinx Introduces Dual 100 Gbps Gearbox Solution</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/cfp2-optical-modules/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/cfp2-optical-modules/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>Altera Stratix V GT FPGA Interoperates with 100-Gbps Optical Module</title>
		<link>http://fpgablog.com/posts/oif-interoperability/</link>
		<comments>http://fpgablog.com/posts/oif-interoperability/#comments</comments>
		<pubDate>Wed, 22 Feb 2012 16:40:23 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[100-Gbps]]></category>
		<category><![CDATA[altera]]></category>
		<category><![CDATA[Interoperability]]></category>
		<category><![CDATA[Networks]]></category>
		<category><![CDATA[OIF]]></category>
		<category><![CDATA[Optical Module]]></category>
		<category><![CDATA[Stratix V GT]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3673</guid>
		<description><![CDATA[Altera recently used their 28nm Stratix V GT FPGA devices to demonstrate interoperability with a 100-Gbps optical module. This is the first time a field programmable gate array has demonstrated interoperability with a 100-Gbps optical module. The Altera Stratix V GT FPGA&#8217;s interoperability with 100-Gbps optical module will enable next-generation 100-Gbps networks. This is of [...]]]></description>
			<content:encoded><![CDATA[<p>Altera recently used their 28nm Stratix V GT FPGA devices to demonstrate interoperability with a 100-Gbps optical module. This is the first time a field programmable gate array has demonstrated interoperability with a 100-Gbps optical module. The Altera Stratix V GT FPGA&#8217;s interoperability with 100-Gbps optical module will enable next-generation 100-Gbps networks. This is of importance because more bandwidth will be required in the next few years because global Internet traffic expected to multiply dramatically.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/oif-interoperability/">Altera Stratix V GT FPGA Interoperates with 100-Gbps Optical Module</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/oif-interoperability/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/oif-interoperability/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>Microsemi RT ProASIC 3 FPGA Devices Ready for Space</title>
		<link>http://fpgablog.com/posts/radiation-cqfp/</link>
		<comments>http://fpgablog.com/posts/radiation-cqfp/#comments</comments>
		<pubDate>Mon, 13 Feb 2012 16:45:05 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[ceramic quad flat pack]]></category>
		<category><![CDATA[CQFP]]></category>
		<category><![CDATA[field programmable gate arrays]]></category>
		<category><![CDATA[FPGAs]]></category>
		<category><![CDATA[Microsemi]]></category>
		<category><![CDATA[radiation-tolerant]]></category>
		<category><![CDATA[RT ProASIC 3]]></category>
		<category><![CDATA[Space]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3649</guid>
		<description><![CDATA[Microsemi&#8217;s radiation tolerant RT ProASIC 3 family of field programmable gate arrays (FPGAs) is now available in a ceramic quad flat pack (CQFP) package. Starting in April 2012, the Microsemi RT ProASIC3 FPGA devices will be available for prototyping in the CQ256 package. Fight units will be available by June 2012. Read more Microsemi RT [...]]]></description>
			<content:encoded><![CDATA[<p>Microsemi&#8217;s radiation tolerant RT ProASIC 3 family of field programmable gate arrays (FPGAs) is now available in a ceramic quad flat pack (CQFP) package. Starting in April 2012, the Microsemi RT ProASIC3 FPGA devices will be available for prototyping in the CQ256 package. Fight units will be available by June 2012.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/radiation-cqfp/">Microsemi RT ProASIC 3 FPGA Devices Ready for Space</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/radiation-cqfp/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/radiation-cqfp/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>LatticeECP3 FPGA Devices in Low Power, High Speed, and Small Packages</title>
		<link>http://fpgablog.com/posts/lattice-semiconductor-latticeecp3/</link>
		<comments>http://fpgablog.com/posts/lattice-semiconductor-latticeecp3/#comments</comments>
		<pubDate>Tue, 24 Jan 2012 17:44:16 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[High-Speed]]></category>
		<category><![CDATA[Lattice Semiconductor]]></category>
		<category><![CDATA[LatticeECP3]]></category>
		<category><![CDATA[Low-Power]]></category>
		<category><![CDATA[Small Packages]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3598</guid>
		<description><![CDATA[Lattice Semiconductor Corporation is offering low power, high speed, and small form-factor versions of their LatticeECP3 FPGA devices. The new packaging helps engineers create power and space limited applications in professional cameras, surveillance cameras, medical imaging, video communication, and small-form-factor wireline and wireless appliances. Prices for the LatticeECP3-17K Mini Device in 328csBGA package start at [...]]]></description>
			<content:encoded><![CDATA[<p>Lattice Semiconductor Corporation is offering low power, high speed, and small form-factor versions of their LatticeECP3 FPGA devices. The new packaging helps engineers create power and space limited applications in professional cameras, surveillance cameras, medical imaging, video communication, and small-form-factor wireline and wireless appliances. Prices for the LatticeECP3-17K Mini Device in 328csBGA package start at $4.95 (in 500K unit volume). Delivery will be in the fourth quarter of 2013.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/lattice-semiconductor-latticeecp3/">LatticeECP3 FPGA Devices in Low Power, High Speed, and Small Packages</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/lattice-semiconductor-latticeecp3/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/lattice-semiconductor-latticeecp3/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>Lattice Semiconductor Acquires SiliconBlue Technologies for $62 Million</title>
		<link>http://fpgablog.com/posts/custom-mobile-device/</link>
		<comments>http://fpgablog.com/posts/custom-mobile-device/#comments</comments>
		<pubDate>Tue, 13 Dec 2011 07:11:45 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[custom mobile device]]></category>
		<category><![CDATA[Handheld]]></category>
		<category><![CDATA[Lattice Semiconductor]]></category>
		<category><![CDATA[Mobile Consumer]]></category>
		<category><![CDATA[mobileFPGA]]></category>
		<category><![CDATA[SiliconBlue Technologies]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3550</guid>
		<description><![CDATA[Lattice Semiconductor will acquire SiliconBlue Technologies for about $62 million in cash. According to Lattice, the acquisition of SiliconBlue is aligned with their strategic long range plan and will help accelerate their growth strategy in the mobile consumer market. Silicon Blue will further strengthen Lattice&#8217;s product roadmap by adding a scalable, low cost, low power [...]]]></description>
			<content:encoded><![CDATA[<p>Lattice Semiconductor will acquire SiliconBlue Technologies for about $62 million in cash. According to Lattice, the acquisition of SiliconBlue is aligned with their strategic long range plan and will help accelerate their growth strategy in the mobile consumer market. Silicon Blue will further strengthen Lattice&#8217;s product roadmap by adding a scalable, low cost, low power nonvolatile memory FPGA, along with key personnel and blue chip customers.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/custom-mobile-device/">Lattice Semiconductor Acquires SiliconBlue Technologies for $62 Million</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/custom-mobile-device/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/custom-mobile-device/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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