Synopsys ReadyIP Flow Reduces Design Time

CAST, Inc. SoC Solutions LLC recently developed a complete 32-bit processor-based system in just three and a half days with the FPGA design capability from Synopsys (Synplicity Business Group). The system is a typical design that uses an ARM® Cortex[tm]-M1 processor and includes all the buses and peripherals needed to run embedded software. SoC Solutions’ engineers estimate it took them less than half the time if would normally have taken them to create the system.

The quicker development was made possible by Synopsys’ new ReadyIP initiative for technology-independent FPGA design. This includes the ReadyIP line of pre-packaged, pre-licensed evaluation cores (supplied by CAST and others) and the new System Designer capability included in the Synplify Pro® and Synplify® Premier FPGA implementation tools, that makes it easy to define and synthesize FPGA systems.

Implemented on a Synopsys HAPS-51 high-speed prototyping system, the demo system ran a live software debugging session complete with two-way communication with a laptop PC through a Hyperterm window. The demo exercised the ARM Cortex-M1 processor and a comprehensive set of AMBA buses and peripherals, including the AHB and APB buses, an AHB to APB Bridge, Memory Controllers, Timer, UART, GPIO, PWM, and external FLASH and SRAM memories. The system infrastructure library used in the demo system (called the PiP-AMBA) was developed by SoC Solutions and is part of the CAST product line.

Synopsys’ ReadyIP program helps designers to easily acquire and integrate evaluation IP from multiple independent providers and target it to devices from multiple FPGA vendors. Suppliers using the ReadyIP flow ensure consistent packaging and interconnection compatibility across the ReadyIP program by using the SPIRIT Consortium’s IP-Xact metadata format. Their valuable IP is protected using the encryption technology with digital rights management (developed by the Synplicity Business Group of Synopsys and now undergoing standardization in the IEEE’s P1735 Working Group). Vendors offer their cores through ReadyIP under simple, click-to-agree evaluation licenses, eliminating the red tape typically surrounding IP use and making possible the “push-button downloads” philosophy behind the ReadyIP program.

More info: Synopsys ReadyIP Program | CAST ReadyIP Cores | Soc Solutions