PCIEXPAIF Application Interface Core for Altera, Xilinx FPGA PCIe Hard IP

CAST announced their PCIEXPAIF IP Core for integrating PCI Express in an FPGA-based system. The IP core includes a high-level interface between system buses like AMBA AXI4 and the PCI Express hard macro blocks available from Altera and Xilinx. The PCIEXPAIF IP Core integrates a completer controller and DMA controller with up to eight DMA channels. The functionality of the DMA controller can be extended using the Scatter-Gather controller. The CAST core supports 32- and 64-bit versions of the open source Wishbone Bus and the AMBA AHB, AXI and AXI4 buses.

CAST PCIEXPAIF IP Core for integrating PCI Express in an FPGA-based system

CAST PCIEXPAIF Application Interface Core Features

  • Transaction Layer Packets (TLP) Encoding/Decoding and Completion Controller for easier system integration
  • Relieves the SoC designer from the complexity of TLP handling
  • Makes integrating PCI Express in a system easier than using other DMA cores for the PCIe Hard IP block
  • Configurable FIFO sizes
  • Up to eight independent DMA channels
  • Functionality of the DMA controller can be extended using the Scatter-Gather controller
  • Control registers accessible from SoC bus and PCIe bus side
  • Interrupt support
  • Interface core supports the 32- and 64-bit versions of the open source Wishbone Bus and the AMBA AHB, AXI and AXI4 buses
  • Altera version is compatible with Altera Cyclone IV GX, Arria II GX, Stratix IV GX, and Stratix V GX devices
  • Xilinx version is compatible with Virtex-5, Virtex-6 and Spartan-6 devices

More info: CAST