Impulse Accelerated Technologies released version 3.7 of their Impulse C and CoDeveloper for compiling C algorithms to Altera’s Quartus revision 12 Qsys software. This enables software developers to more easily compile C based algorithms for the fastest integration into Altera Stratix and Cyclone FPGAs. According to Impulse, project managers report 50% time savings on first prototype and more than 80% time savings on iterations using the Impulse C tool to Quartus tool flow.
Software developers increasingly use FPGAs to accelerate compute-bound microprocessor algorithms. However, they frequently encounter three problems:
- Most software developers are not familiar with VHDL, Verilog and hardware design in general
- Most do not fully understand the nature of hardware resources on FPGA no less on an FPGA based development board
- Most cannot readily partition code between running on FPGA hardware and running, often over PCIe, on the host processor
Impulse C 3.7 bridges these gaps by adding an interface between C algorithms and hardware resources that readily integrates within Qsys and Quartus. This lets a software developer refactor microprocessor oriented C into coarse-grained logic, that is easily machine-parallelized into multiple streaming processes. These processes run in FPGA hardware or are partitioned to run native on the host processor, or on available processor cores from Altera. The cross-compiled code remains fully ANSI C compatible so it can be simulated within standard tools such as MS Visual Studio. For cycle-accurate HDL verification, Impulse C also provides a direct export of a test bench to Mentor ModelSim or Aldec Active HDL.
More info: Impulse Accelerated Technologies