Lattice HiGig MAC IP Core for LatticeECP3 FPGA Devices

Lattice Semiconductor introduced the HiGig MAC IP core for their low cost LatticeECP3 FPGA family. The HiGig MAC IP ensures that the Media Access rules specified in the 802.3ae IEEE standard and HiGig Protocol definitions are met while transmitting a frame of data over Ethernet. The core also extracts the different components of a frame and transfers them to higher applications through a FIFO interface. With the HiGig MAC IP core, designers can implement low cost network solutions using Broadcom devices. The Lattice HiGig MAC IP core is available now for a list price of $5,000.

Lattice Semiconductor HiGig MAC IP core for LatticeECP3 FPGA family

Lattice HiGig MAC IP Core Features

  • Compliant to the Broadcom HiGig and HiGig2 Protocol Definitions
  • 64-bit wide internal data path operating at a maximum frequency of 187.5 MHz (LatticeECP3 maximum 156 MHz)
  • XGMII interface to the PHY layer (using IODDR external to the core)
  • XAUI interface to the PHY layer (using PCS/SERDES external to the core)
  • Simple FIFO interface with user’s application
  • Optional multicast address filtering
  • Transmit and receive statistics vector
  • Optional statistics counters of length from 16 to 40 (external to the core)
  • Variable-sized packet transmission with fixed sized messaging capability (HiGig2 Only)
  • Programmable Inter Frame Gap
  • Supports:
    • Full duplex operation
    • Flow control using PAUSE frames (for HiGig) and messaging (for HiGig2)
    • Automatic padding of short frames
    • Optional FCS generation during transmission
    • Optional FCS stripping during reception
    • Jumbo frames up to 16k
    • Inter frame Stretch Mode during transmission
    • Deficit Idle Count

More information: Lattice Semiconductor