SCE-MI: Enabling Faster IP Verification with Emulation and FPGA Prototyping

Bluespec is offering a webinar entitled “SCE-MI: Enabling Faster IP Verification with Emulation and FPGA Prototyping.” The webcast introduces SCE-MI (Standard Co-Emulation Modeling Interface), which is the industry standard for co-emulation. The SCE-MI standard makes connecting software testbenches with hardware emulations and FPGA prototypes much easier.

The one hour webinar will held on Wednesday, November 19, 2008 at 2:00pm EST (GMT -05:00, New York). Rishiyur S. Nikhil, chief technology officer of Bluespec, will host.

Webinar Topics

  • SCE-MI’s architecture, capabilities and typical use models
  • Performance considerations for co-emulation
  • How SCE-MI will be used in the future and what automation will be required beyond SCE-MI
  • How SCE-MI eliminates the complexity of connecting software and testbenches with emulation platforms and FPGA-based boards
  • How SCE-MI accelerates verification and software debug
  • How SCE-MI promotes infrastructure portability and re-use

Description
As chip verification and software development monopolize more of the development cycle, simulation has become a fundamental bottleneck. Emulation and FPGA prototyping promise relief, but they have a reputation for being expensive, hard to setup and manage, and prone to significant testbench performance bottlenecks. SCE-MI (Standard Co-Emulation Modeling Interface) will help change this. SCE-MI is a standardized interface for co-emulation of a software testbench with a hardware model running in an emulation system or on an FPGA prototype. The SCE-MI 1.0 standard handles the data exchange between software and hardware as well as clock control of the design in emulation. Supported by most emulation providers, SCE-MI should greatly simplify emulation and FPGA prototyping – and make them significantly more accessible.

More info: SCE-MI: Enabling Faster IP Verification with Emulation & FPGA Prototyping