Altera introduced a high-definition (HD), intellectual property (IP) reference design for surveillance cameras on a single FPGA. The reference design features Altera’s Cyclone III or Cyclone IV FPGAs and IP from Eyelytics and Apical supporting AltaSens’ 1080p60 A3372E3-4T and Aptina’s 720p60 MT9M033 HD Wide Dynamic Range (WDR) CMOS image sensors. The solution reduces board space, lowers power consumption, increases flexibility and reduces development time compared to previous architectures using traditional digital signal processors and ASSPs.
Altera HD Surveillance IP Camera Reference Design Functions
- Hot pixel removal and WDR sensor demosaic functions
- A complete Image Signal Processor (ISP): including color pipeline, auto white balance and auto exposure (including exposure mixing for WDR)
- Apical’s spatial dynamic range-compression (local tone mapping) algorithm, known as “iridix”
- Apical’s 2D noise-reduction algorithm, known as “sinter”
- Eyelytics’ H.264 video encoder, capable of 720-line progressive 30 frames-per-second encoding or 1080-line progressive 15 frames-per-second encoding in main profile
- Altera’s Triple-Speed Ethernet MAC IP and Nios II embedded processor cores
Hardware for the Reference Design Includes Aptina’s MT9M033 720p WDR CMOS Image Sensor, the Cyclone III FPGA Development Kit, and Bitec’s DVI HSMC Daughtercard. The bundling of a comprehensive list of IP in this reference design gives designers a head start in camera development, shortening development time by as much as one year. All camera designers have to do is customize the FPGA with their own specific features, such as adding their own software for motion detection, and pan, tilt and zoom control.