Xilinx and BEEcube Inc. announced a high-performance development environment for multi-core UltraSPARC CMT (chip multi-threaded) processors that reduces the time and effort required to design systems using the SPARC architecture. The platform enables researchers and hardware architects to quickly experiment with large scale, multi-core, multi-threaded FPGA implementations of UltraSPARC CMT processors for a broad set of end-markets including computing, industrial, scientific, medical, aerospace and defense, storage, and networking. The BEE3-based OpenSPARC FPGA development platform is immediately available through BEEcube. University discounts and software donations are available through the Xilinx University Program and BEEcube Academic Discount program.
The BEEcube SoC development platform features the BEE3 large-scale multi-core processor emulator and takes full advantage of the performance and flexibility of Xilinx’ flagship Virtex-5 FPGAs. The new platform is ideal for designers who wish to evaluate the capabilities of the SPARC CMT architecture in a programmable device. The BEEcube SoC development platform enables system architects using the SPARC CMT architecture to rapidly explore design trade-offs for cost/power/performance optimizations.
A single BEE3 module is capable of emulating either a quad-core 16-thread or two dual-core 8-thread UltraSPARC T1 processors, running on a binary-compatible OpenSolaris or Ubuntu Linux operating system. Each BEE3 module is designed using the latest Virtex-5 FPGAs. Existing users have a migration path from the Virtex-5 OpenSPARC single-FPGA Evaluation Platform to the new BEE3 quad-FPGA scalable computing platform. The new BEEcube development system offers researchers and hardware architects six times more FPGA logic capacity, 64 times larger DRAM capacity, and support for PCI Express x8 and 10-Gigabit Ethernet interfaces.