Avnet Electronics Marketing announced the Xilinx Spartan-6 FPGA DSP Development Kit. The Avnet DSP kit includes a device-locked version of ISE Design Suite: System Edition 11.4. Design flows using MATLAB and Simulink is included as part of the Xilinx Spartan-6 FPGA Kit. Model-Based Design using Simulink eases the adoption of FPGAs and accelerates FPGA implementation of signal processing, computer vision and control system applications. With Xilinx System Generator it provides a turnkey rapid prototyping solution for engineers new to FPGAs without RTL design experience. The Xilinx Spartan-6 FPGA DSP Development Kit is priced at $1,995.
Avnet Spartan-6 FPGA DSP Development Kit Highlights
- Xilinx Spartan-6 LX150T board
- Design source files for RTL and Simulink
- Top level system integration RTL source files
- Implementation environment
- Complete steps and parameters for design synthesis
- MAP, place and route and timing closure
- Targeted reference design tutorials including recommended flows for design modification and integration
- 12 V power supply
- USB-II JTAG programming cable
- USB A to USB B cable
- Ethernet cable
- Xilinx ISE Design Suite 11.4 System Edition Software (device locked to LX150T)
- Includes EDK and System Generator for DSP
- The MathWorks Simulink evaluation tools
The Spartan-6 FPGA DSP Development Kit combines a scalable development board, DSP IP, DSP Development tools, and a preconfigured and fully validated Spartan-6 DSP Targeted Reference Design. This design serves as a basis to illustrate DSP techniques and design flows for the Spartan-6 class of signal processing functions. The state of the art digital up converter (DUC) / digital down converter (DDC) Targeted Reference Design shows customers how to use advanced techniques such as clock over-sampling, time division multiplexing and signal processing and resource optimization with the high performance DSP48 slices.
Both an RTL and Model-Based Design flows are included. The design flow, based on MATLAB and Simulink from the MathWorks, allows algorithm developers to create DSP hardware designs using a familiar modeling environment without the need to learn RTL. Experienced RTL designers are provided design techniques for creating efficient DSP hardware using ISE Design Suite and LogicCore DSP IP along with verification methodologies for comparing functional correctness against high-level algorithm models.
More info: Avnet Electronics Marketing