Avnet to Conduct FPGA Seminars at Embedded Systems Conference

Avnet Electronics Marketing Americas will conduct FPGA design seminars for engineers at the Embedded Systems Conference (ESC), running April 14-18 at San Jose’s McEnery Convention Center.

On Tuesday and Wednesday, Avnet Field Application Engineer R.C. Cofer and SAIC Senior Systems Engineer Ben Harding will provide two two-part presentations on hardware design and programmable logic. Their first presentation series, “Introduction to CPLD and FPGA Design, Part 1 & 2,” examines underlying architectures, resources, tools and design flow steps for Complex Programmable Logic Devices (CPLD) and Field Programmable Gate Array (FPGA) devices.

Cofer and Harding’s second series, “Implementing Processors and DSP Functionality within FPGAs, Part 1 & 2,” provides a how-to for implementing processor and Digital Signal Processor (DSP) functions into FPGA devices. Engineers will leave the sessions armed with a comprehensive understanding of CPLD and FPGA and the knowledge of how to design them into systems. In addition, the sessions will cover critical design decisions and effective techniques for implementing embedded processor and DSP system functions into FPGA devices.

In addition, Avnet Technology Specialist Jim Carver will present “Selecting a Microcontroller for Your Power Constrained Application” on Monday, April 14. His presentation highlights tips for analyzing specific application needs and operating characteristics of microcontrollers to assist engineers in making informed choices when to select the best solutions to meet their design application needs.

More info: Avnet Electronics Marketing