TEK Microsystems QuiXilica Atlas-V5 VXS Digitizer Board

TEK Microsystems introduced the QuiXilica Atlas-V5 VXS product. The Atlas-V5 features eight channels of 12-bit 1 Gsps (Gigasamples per second) analog inputs streaming up to 12 GB/s into three Xilinx Virtex 5 FPGAs in a single 6U VME / VXS slot. The Atlas-V5 supports 1 Gsps ADC devices with 12 bits of resolution, enabling unprecedented performance for multi-channel applications (such as beamforming, Radar, SIGINT, COMINT and wireless communications). The Atlas-V5 is available now.

TEK Microsystems QuiXilica Atlas-V5 VXS Digitizer Board

Xilinx Virtex-5 FPGAs are the heart of the Atlas-V5. The FPGAs interface between the ADCs, memory and I/O resources to provide a platform for implementing high performance real time processing. The Atlas-V5 is configured with two SX95T FPGAs and one LX110T FPGA. An LX220T, SX240T, or FX100T FPGA can be selected to match resources to the application. All FPGAs are interconnected by wide parallel LVDS busses and via high speed serial links using the Xilinx Rocket IO MGTs.

The front end FPGAs each accept four channels of input data for initial processing. The outputs of the front end FPGAs (up to 6 GB/s each) are then combined in the back end FPGA for additional processing and output via the VXS backplane or front panel QSFP fiber optic links at aggregate rates up to 3.75 GB/s. When configured with an SX240T back end FPGA, the Atlas-V5 delivers 2,336 V5 DSP slices with up to 1.3 TeraMAC/s of signal processing capability.

QuiXilica Atlas-V5 VXS Features

  • Eight Channels: 12-bit ADC Input at 1 Gsps Each
  • Sample Accurate Synchronization Across Multiple Boards
  • High Channel Count, Low Latency Data Routing and Large / Fast FPGA Processing
  • All eight ADCs Clocked from a Common Input, or Two Independent Clock Inputs for Groups of Four ADC channels
  • Six Digital IO Channels Running at Up to 3.75 Gb/s Using One QSFP and Two SFP+ Front Panel Connections
  • Dual 4x Full Duplex VXS Links and Two Full Duplex VITA 41.6 Ethernet Links
  • Three Xilinx Virtex-5 FPGAs: LXT, SXT or FXT for Each Location
  • Three GB DDR3 SDRAM Memory, (one GB per FPGA)
  • Advanced Temperature and Current Monitoring
  • Comprehensive Developer’s Kit Provided Including FPGA Interface Cores, QuiXtart FPGA Utilities, Software and Reference Design
  • Convection or Conduction Cooled

More info: TEK Microsystems