eBook: Testing System Clocks with Boundary Scan (JTAG) and an FPGA

Testing System Clocks with Boundary Scan (JTAG) and an FPGA

ASSET InterTech published a new ebook that explains how cost-effective verification of system clocks during prototype circuit board bring-up and manufacturing can be accomplished with several different methods based on JTAG and boundary-scan testing or IP in an FPGA. The title of the ebook is Testing System Clocks with Boundary Scan (JTAG) and an FPGA.

Testing System Clocks with JTAG and an FPGA Topics

  • Testing clocks without probes
  • Boundary scan put to good use
  • JTAG and FPGA IP instruments
  • Testing functionality of slow clocks

The ASSET InterTech eBook explains how system clocks can be tested with simple, yet cost-effective and powerful methods based on non-intrusive embedded instruments.

Faulty clocks will simply prevent processors, chipsets, ASICS, FPGAs and all other functional devices from bringing up their operational states. As a result, the operating system and the system’s firmware environment will not boot. By quickly verifying the functionality of the clocks first or relatively early, the engineer can reduce the time needed to bring up prototypes and allow adequate time for more robust functional testing during manufacturing.

More info: Testing System Clocks with Boundary Scan (JTAG) and an FPGA