Aldec Riviera-PRO 2008.10 HDL Design Simulator for FPGA Designs
Aldec, Inc. released Riviera-PRO 2008.10 behavioral and structural HDL mixed-language simulator for multi-million gate ASIC and FPGA designs. Riviera-PRO 2008.10 features a powerful new multi-threaded Graphical User Interface (GUI) with post-simulation debugging, SystemC/C/C++ and HDL co-debugging, support for SVA/PSL/OVA Assertions, and Functional Coverage in the Waveform Viewer. Riviera-PRO 2008.10 is available today in three Product Configurations.
Riviera-PRO is a common-kernel, mixed language, multi-platform simulator for Verilog, SystemVerilog, VHDL, SystemC/C/C++, Assertions and EDIF. It supports System Level Verification with SystemC and SystemVerilog, Assertion-based Verification, Electronic System Level (ESL), Transaction Level Modeling (TLM) and STARC® based Linting. Riviera-PRO works in command line mode for maximum speed and includes enhanced editing, tracing, debugging capabilities and Code Coverage. Riviera-PRO is compatible with popular EDA products such as Synopsys® SmartModels[tm], Novas[tm], Denali®, MATLAB® and Simulink®.
Riviera-PRO 2008.10 Features
64-bit Multi-Threaded Design Environment
Riviera-PRO 2008.10 features a GUI that is based on 32/64 bit architecture and supports multi-threading with multi-core processor support, operating at 60% faster speeds. With the new multi-threaded GUI, engineers can now multi-task during simulation, running HDL simulation while working on code or other tasks. Riviera-PRO 2008.10′s new GUI now provides an enhanced Waveform Viewer, support for multi-design workspaces, Tcl scripting, improved Hierarchy Navigation, memory allocation reduction, all from an entirely new user-friendly tabular/multi-document framework.
Post-Simulation Debugging Features
Riviera-PRO 2008.10 provides an additional mixed-language, post-simulation debugging mode that not only displays signal waveforms, but also provides engineers access to a full post-debugging toolset. After opening a simulation dataset that encompasses hierarchy and simulation databases offline, engineers can perform design debugging at any time after simulation.
Co-Debugging of SystemC/C/C++ in HDL
Riviera-PRO 2008.10 offers a new level of integration where pure SystemC designs and mixed HDL-SystemC designs can be debugged using one unified HDL environment. Engineers can set breakpoints both in HDL code and in C++ code, or step through HDL and SystemC statements in the same editor. Additional co-debugging tools show both HDL and SystemC hierarchy and values of HDL. SystemC objects and the call stack can be examined both for HDL subprograms and C/C++ function calls.
Assertions and Functional Coverage Support
The new release provides dedicated Assertion and Cover Viewer, which dramatically increases visibility of assertions and covers, enabling their direct, graphical display in a Waveform Viewer. Riviera-PRO allows direct access to design hierarchy browser, simulator console, Code Coverage and breakpoint settings. Assertion and Cover statements may be “dragged-n-dropped” from the Assertion Viewer directly into the Waveform Viewer.
Enhanced Language Support
Riviera-PRO now includes support for the new VHDL Standard and IEEE Std 1076[tm]-2008 and the enhanced IEEE 1800TM SystemVerilog.
More info: Aldec
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