Thanks to expanded support for the Universal Verification Methodology (UVM) with comprehensive transaction-level visual debugging, engineers can now use Riviera-PRO 2011.06 advanced debugging infrastructure without having to manage basic mechanisms for transactions handling. Aldec Riviera-PRO is an ideal verification platform for building up layered, coverage driven, constrained-random environments for functional verification of ASIC and FPGA designs.
Aldec’s UVM 1.0 implementation combines the debugging capabilities of Riviera-PRO with an industry-standard approach to building reusable and expandable verification environments. As a result, engineers have a more natural way for engineers to comprehend and debug sophisticated verification environments.
Riviera-PRO supports the latest versions of industry standard verification libraries such as SystemVerilog UVM 1.0, OVM 2.1.2 and VMM 1.1.1a. The new UVM 1.0 transaction-level debugging capabilities are available now in the latest release of Riviera-PRO 2011.06. There is no addition cost to engineers with a valid maintenance contract and SystemVerilog verification support.
With Riviera-PRO, transaction data can be analyzed with the existing Waveform Viewer tool and the new Transaction Data Viewer that represents transactions as a spreadsheet that offers rich navigation and filtering capabilities. All the debugging tools are well integrated with each other and allow for efficient analysis of transaction-level information, including the cross-probing and viewing of transaction attributes, relations and linked signals. Based on such a broad range of information about the interactions between testbench and design under test, Riviera-PRO users have extensive visibility into their verification environments.
More info: Aldec