Chip Path Semiconductor IP Centric Design for ASIC, FPGA, ASSP

Chip Path Design Systems introduced their new approach to semiconductor IP chip design. Their methodology focuses on a common Semantic-IC Specification with the ability to map to multiple implementation styles and understanding of complete project costs. Their Semiconductor IP Centric Design results in visibility of timelines and costs across ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), and production-ready ASSP (Application Specific Standard Product) devices.

Chip Path Semiconductor IP Centric Design for ASIC, FPGA, and ASSP

Semiconductor IP Centric Design for ASIC, FPGA, and ASSP Highlights

  • Enables the evaluation of thousands of FPGA devices and thirteen SoCs (Systems-on-Chip)
  • Reduces implementation time with seamless transition to the design phase
  • Semiconductor IP Design distills into three main design components: I/O Channels, Subsystems, and NoC (Network-On-Chip)
  • Components are then selected based on requirements and implementation
  • Specifications can run through a RFQ Compiler (Request-for-Quote) mapping architecture onto ASIC technology choices and FPGA devices from vendors like Xilinx, Altera, Lattice
  • Specification can be evaluated against existing ASSP products such as TIs OMAP, Atmel’s microcontrollers
  • Chip Path’s databases include models for Semiconductor IP with over 14,000 entries, IC-Technologies from 14nm to 0.35um (13 nodes), and over 9,000 FPGA devices
  • Chip level integration is simplified by moving up to an I/O Channel level of abstraction
  • Off-chip interfaces are modeled as connectors (PCIe, DDR3, CAN, Interlaken, and about 80 others)
  • Channels are simply collections of IP that go from I/O Connectors to one or more, on-chip bus connectors
  • Chip Path’s on-chip connector based assembly approach enables rapid integration of ASIC and FPGA
  • Each IP has one or more connectors using protocols like AMBA, AXI4, OCP-IP, Wishbone, Avalon, and only about 8 others
  • Semiconductor IP Methodology defines an IPCN (IP Connection Network) integrating the entire chip
  • IPCN has multiple levels, including clock, reset, test, interrupt, point-to-point networks, with the NoC (Network-on-Chip) or Bus-Fabric remaining the central connectivity paradigm
  • Connectors allow Memory Mapped (MM) or Streamed (ST) interfaces along with point-to-point hookup
  • Chip Path’s catalog features over 1,200 IP with NoC connectors

More info: Chip Path Design Systems